Self-Aligned Gate Endcaps Without Fin End Gaps
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Solution Overview
Problem
The scaling of multi-gate transistors in semiconductor devices poses challenges due to constraints on lithographic processes, leading to trade-offs between feature dimension and spacing, and resulting in issues such as fin end gaps and decreased device yield.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures without fin end gaps, achieved through selective growth of germanium spacers to form SAGE walls that directly abut fin ends, eliminating the need for extra endcap length to account for mask registration errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern transistor features, then feature dimensions can be reduced, but spacing between features must be increased to accommodate mask registration errors
Solution Approach 1:
The patent applies preliminary action by forming the gate endcap isolation structure before final gate patterning. The SAGE wall is created in advance using selective epitaxial growth on exposed semiconductor surfaces at fin ends, establishing a self-aligned reference structure that eliminates the need for additional spacing to accommodate mask registration errors during subsequent lithographic steps.
Solution Approach 2:
The patent implements self-service through self-aligned gate endcap formation. The selectively grown isolation structure automatically positions itself at the fin ends without requiring additional lithographic alignment, as the epitaxial growth occurs only on exposed semiconductor surfaces. This self-alignment mechanism eliminates dependency on mask registration precision.
2Reliability
If extra endcap length is added to account for mask registration errors, then spacing requirements are relaxed, but device layout density decreases
Solution Approach 1:
The gate endcap isolation structure serves itself by automatically positioning at fin ends through selective epitaxial growth. The structure forms only on exposed semiconductor surfaces without requiring external alignment references, thereby eliminating the need for extra endcap length while maintaining reliability against mask registration errors.
Solution Approach 2:
The patent replaces the mechanical alignment system (lithographic mask registration) with a chemical self-assembly mechanism (selective epitaxial growth). The isolation structure forms through material science principles rather than mechanical positioning, substituting a precision mechanical process with a self-organizing chemical process that inherently achieves atomic-level alignment.
3Ease of manufacture
If fin end gaps are present in the structure, then manufacturing is simpler, but device yield and electrical parameter consistency decrease
Solution Approach 1:
The patent applies local quality by creating a differentiated structure where the gate endcap isolation structure is present only at specific locations (fin ends) rather than uniformly throughout. The selective epitaxial growth ensures the isolation structure forms only where semiconductor surfaces are exposed, providing localized correction of fin end gaps without complicating the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more aggressive scaling of diffusion to diffusion spacing, improves transistor layout density, and reduces device to device variability in electrical parameters by eliminating fin end gaps and enhancing gate to contact shorting margin.
Implementation Method 1
selective growth of germanium spacers to form SAGE walls
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure is in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.