Self-Aligned Gate Endcaps for GAA Transistor Scaling
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in scaling down transistor dimensions while maintaining effective diffusion spacing and reducing gate endcap overlap, which is limited by lithographic patterning and registration errors, leading to increased gate capacitance and energy consumption.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, where disposable spacers are used to define gate and trench contact endcaps, eliminating the need for extra endcap length to account for mask mis-registration and allowing for more aggressive diffusion spacing without requiring advanced lithographic patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional lithographic patterning is used to define gate endcaps, then manufacturing process is simpler, but gate endcap overlap increases leading to higher gate capacitance and energy consumption
Solution Approach 1:
The patent introduces an intermediary self-aligned gate endcap structure that acts as a mediator between the gate electrode and the substrate. This endcap structure is formed through a separate deposition process rather than lithographic patterning, allowing precise control of the endcap dimensions and position. The intermediary structure eliminates the need for aggressive lithographic scaling while reducing gate capacitance by optimizing the endcap geometry.
Solution Approach 2:
The self-aligned gate endcap structure utilizes the gate electrode itself as a reference for positioning the endcap. The endcap is deposited conformally on the gate structure, automatically aligning itself without requiring additional lithographic steps or registration processes. This self-service approach achieves precise alignment and reduces manufacturing complexity.
2Productivity
If diffusion spacing is reduced to increase layout density, then device density increases, but lithographic registration errors increase leading to manufacturing variability
Solution Approach 1:
The patent transitions from two-dimensional lithographic patterning to three-dimensional self-aligned deposition for forming gate endcaps. By depositing material conformally on the gate structure, the endcap dimensions and positions are defined in the vertical dimension rather than through lateral lithographic patterning. This dimensional shift enables reduced diffusion spacing without being constrained by lithographic registration errors.
3Use of energy by moving object
If gate endcap overlap is minimized to reduce capacitance, then energy consumption decreases, but manufacturing complexity increases due to additional alignment requirements
Solution Approach 1:
The self-aligned gate endcap structure utilizes the gate electrode itself as a reference for positioning the endcap. The endcap is deposited conformally on the gate structure, automatically aligning itself without requiring additional lithographic steps or registration processes. This self-service approach achieves precise alignment and reduces manufacturing complexity.
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.