Self-Aligned Gate Endcaps for Tighter GAA Diffusion Spacing
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to achieve tighter diffusion end-to-end spacing in ultra-scaled processes while maintaining device performance and density, which is hindered by lithographic limitations and increased gate capacitance.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures with gate-all-around devices, where a disposable spacer is used to determine gate endcap and contact overlap dimensions, allowing for self-aligned gate and trench contact endcaps without requiring extra length for mask registration, thereby reducing device variability and enabling more aggressive scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern semiconductor features, then device dimensions can be reduced, but the spacing between features must be maintained at larger values due to lithographic limitations
Solution Approach 1:
The gate endcap isolation structure is formed preliminarily before the gate electrode is deposited. This preliminary formation of the isolation structure at the gate ends enables subsequent gate patterns to be placed closer together without requiring large spacing for mask registration, as the endcaps are already in place to define the gate boundaries.
Solution Approach 2:
The gate endcap isolation structure acts as an intermediary element between adjacent gate electrodes. By providing this isolation structure at the gate ends, the patent enables tighter spacing between gates while maintaining proper electrical isolation and definition, effectively mediating the spacing requirement.
2Manufacturing precision
If gate endcaps are formed with conventional alignment methods, then mask registration error requires extra length, but this increases device area and reduces density
Solution Approach 1:
The gate endcap isolation structure is formed using a self-aligned process where the isolation structure automatically positions itself relative to the gate pattern. This self-alignment eliminates the need for additional mask registration margins, as the endcaps are defined by the same lithographic pattern that defines the gate electrodes, thereby reducing device area while maintaining precision.
3Productivity
If diffusion spacing is reduced to increase density, then layout density improves, but device variability in electrical parameters increases
Solution Approach 1:
The gate endcap isolation structure provides localized electrical isolation and field control at the critical gate end regions. By concentrating the isolation function at the gate ends rather than requiring uniform spacing throughout, the patent enables reduced diffusion spacing while maintaining proper electrical characteristics and reducing variability through localized field management.
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.