Self-Aligned Gate and Field Plate Layout for Low-Capacitance GaN HFETs
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Solution Overview
Problem
There is a need for semiconductor devices, such as GaN HFETs, with smaller gate-to-field plate spacing to reduce gate-to-drain capacitance, as conventional manufacturing methods face limitations in achieving such small spacings without electrical shorts.
Innovation Solution
The solution involves using a single patterned photoresist mask to form simultaneously the source, drain, gate, and field plate openings through a lower dielectric layer, and then depositing a conformal dielectric layer into these openings. This approach allows for self-aligned formation of the gate and field plate electrodes, enabling a very small gate-to-field plate spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing methods are used to form gate and field plate electrodes, then the fabrication process is simpler, but the gate-to-field plate spacing cannot be reduced below a certain limit due to electrical shorts
Solution Approach 1:
The patent combines the formation of gate and field plate openings into a single photolithography step using one patterned photoresist mask. This merging of previously separate fabrication steps enables precise spatial alignment between the gate and field plate electrodes, allowing the gate-to-field plate spacing to be reduced to less than 0.5 micrometers without causing electrical shorts, thus resolving the contradiction between manufacturing precision and reliability
Solution Approach 2:
The single patterned photoresist mask serves multiple functions simultaneously: it defines both the gate opening and the field plate opening in a self-aligned manner. The mask's pattern automatically establishes the precise relative positioning of the two electrodes, eliminating the need for separate alignment steps and enabling minimal spacing while preventing electrical shorts
2Loss of energy
If the dielectric layer thickness is reduced to decrease gate-to-drain capacitance, then the device performance improves, but electrical shorts occur between gate metal and field plate using conventional methods
Solution Approach 1:
By merging the formation of gate and field plate openings into a single photolithography step, the patent ensures precise spatial alignment that maintains adequate separation between the electrodes even when the dielectric layer thickness is reduced. This allows the dielectric layer to be made thinner to reduce gate-to-drain capacitance while preventing electrical shorts through the self-aligned opening formation
3Manufacturing precision
If multiple separate photolithography steps are used to form gate and field plate openings, then alignment is easier to control, but the gate-to-field plate spacing increases
Solution Approach 1:
The patent merges multiple photolithography steps into a single step where one patterned photoresist mask simultaneously defines both the gate opening and the field plate opening. This self-aligned approach eliminates cumulative alignment errors from multiple steps while precisely controlling the relative positioning, thereby reducing the gate-to-field plate spacing to less than 0.5 micrometers
4Productivity
If the gate-to-field plate spacing is reduced to improve device performance, then gain and linearity improve, but conventional fabrication cannot achieve such small spacings
Solution Approach 1:
The single patterned photoresist mask performs the self-service function of automatically establishing precise spatial relationships between the gate and field plate openings. This self-aligned formation method enables the fabrication of structures with gate-to-field plate spacing of less than 0.5 micrometers, achieving the small spacings needed for improved device performance that were previously unattainable with conventional fabrication methods
Data Source
AI summary
An embodiment of a semiconductor device includes a semiconductor substrate and one or more lower dielectric layers on the surface of the substrate. Source, drain, gate, and field plate openings, which are formed in a self-aligned manner, extend through the lower dielectric layer(s) to the substrate. A conformal dielectric layer is disposed over the lower dielectric layer(s) and into the gate and field plate openings. The conformal dielectric layer includes first portions on sidewalls of the gate opening, second portions on sidewalls of the field plate opening, and a third portion on the substrate at a bottom extent of the field plate opening. Gate spacers are formed on the first portions of the conformal dielectric layer. A gate electrode in the gate opening contacts the gate spacers and the semiconductor substrate. A field plate in the field plate opening contacts the second and third portions of the conformal dielectric layer.