Self-Aligned Gate GaN HEMT Using Single Mask
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Solution Overview
Problem
Conventional enhancement mode GaN transistors require separate photo masks for defining gate metal and p-type GaN or AlGaN material, leading to increased manufacturing costs, wider gate length, higher on-resistance, and high electric field reliability risks at the gate corner.
Innovation Solution
A self-aligned gate structure is achieved by patterning and etching gate metal and doped GaN or AlGaN material using a single photo mask, with the source ohmic contact serving as a field plate to reduce electric fields and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate photo masks are used for defining gate metal and p-type GaN or AlGaN material, then manufacturing precision can be maintained, but manufacturing cost increases and gate length becomes wider
Solution Approach 1:
The patent combines the patterning of gate metal and p-type GaN or AlGaN material into a single photo mask process. The photo mask simultaneously defines both the gate metal region and the p-type doped region, eliminating the need for separate alignment steps. This merging of operations reduces manufacturing cost while maintaining precision through self-alignment of the gate structure.
2Manufacturing precision
If separate photo masks are used for defining gate metal and p-type GaN or AlGaN material, then alignment can be achieved, but gate length increases and on-resistance increases
Solution Approach 1:
By using a single photo mask to define both gate metal and p-type doped region, the patent achieves self-aligned gates with minimal gate length. The gate metal and doped region are patterned together, eliminating the cumulative alignment errors that would occur with separate masks, thereby minimizing the effective gate length and reducing on-resistance.
3Ease of manufacture
If conventional gate structure is used, then device can be fabricated, but high electric field at gate corner causes high gate leakage current and reliability risk
Solution Approach 1:
The patent modifies the gate structure by adding a field plate extension at the gate corner region. This local structural modification redistributes the electric field density, specifically reducing the peak electric field at the gate corner where it would otherwise be concentrated. The field plate creates a more gradual field distribution, reducing gate leakage current and improving reliability while maintaining overall fabrication simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, minimizes gate charge, lowers on-resistance, and enhances gate reliability by reducing gate leakage current and electric field stress, while maintaining control over the device's operation.
Implementation Method 1
The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers
Implementation Method 2
the source ohmic contact serving as a field plate to reduce electric fields and improve reliability
Data Source
AI summary
An enhancement-mode GaN transistor. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.