Self-Aligned Gate MOS Transistor Using 2D Semiconductor
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Solution Overview
Problem
Existing methods for manufacturing MOS transistors using two-dimensional semiconductor materials, such as MoS2, require multiple photolithography steps, leading to a non-self-aligned gate structure that increases the transistor size due to gate extension over source and drain regions.
Innovation Solution
A method involving a sacrificial grid and spacers allows for self-aligned source and drain formation, followed by deposition and planarization to ensure the gate is aligned with these regions, reducing overall transistor size by eliminating unnecessary material outside the channel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple photolithography steps are used to define source/drain and gate regions separately, then the transistor can be manufactured with conventional processes, but the gate extends over source and drain regions increasing the overall transistor size
Solution Approach 1:
A sacrificial grid is formed in advance at the desired gate position before depositing the two-dimensional semiconductor material. This preliminary structure guides the subsequent self-aligned formation of source and drain regions, ensuring the gate will be precisely positioned without requiring post-alignment photolithography steps.
Solution Approach 2:
The sacrificial grid and spacer structure enable the source and drain regions to self-align with the gate region during the deposition process. The two-dimensional semiconductor material naturally conforms to the spacer-defined boundaries, automatically positioning the channel region between source and drain contacts without additional alignment steps.
2Area of stationary object
If the gate is self-aligned with source and drain regions, then the overall transistor size is reduced, but the manufacturing process becomes more complex requiring sacrificial structures
Solution Approach 1:
The sacrificial grid acts as an intermediary structure that temporarily occupies the gate position during manufacturing. It mediates between the source/drain contact formation and the final gate electrode deposition, enabling precise alignment without requiring complex photolithography alignment procedures. The spacer material serves as another intermediary that defines the channel region boundaries.
Solution Approach 2:
The sacrificial grid material is selectively removed after defining the gate region boundaries, extracting the alignment guidance function from the final device structure. This allows the gate electrode to be deposited precisely in the intended location without the sacrificial material remaining in the finished transistor.
3Productivity
If two-dimensional semiconductor material is exposed to multiple processing steps, then complete transistor fabrication is achieved, but the sensitive material is exposed to increased risk of damage
Solution Approach 1:
The sacrificial grid and spacer structures are formed before depositing the two-dimensional semiconductor material, establishing all alignment references in advance. This preliminary preparation allows the sensitive material to be deposited once and then processed through minimal subsequent steps, reducing cumulative exposure to potential damage sources.
Solution Approach 2:
The two-dimensional semiconductor material serves its dual function as both the structural channel element and the alignment reference for source and drain contacts. The material's own geometry, defined by the spacer boundaries during deposition, provides the alignment information needed for subsequent processing, eliminating the need for separate alignment steps that would increase exposure risk.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more compact transistor design with a self-aligned gate, reducing the overall size and simplifying interconnections, while minimizing exposure and risk to sensitive two-dimensional semiconductor materials during processing.
Implementation Method 1
The atoms or molecules within the same sheet are relatively strongly bonded by covalent bonds
Implementation Method 2
the atoms or molecules in neighboring sheets are relatively weakly bonded by Van der Waals forces
Data Source
Figure 1A~1D
Figure 1E~1H
Figure 2~3B
AI summary
The invention relates to a method for manufacturing a MOS transistor, comprising: a) forming a first conductive or semiconducting layer (105); b) forming a sacrificial gate on the first layer, and a second layer (111) of an insulating material laterally surrounding the sacrificial gate; c) forming, on either side of the sacrificial gate, electrical connection elements (115) of source and drain passing through the second layer (111) and contacting the first layer (105); d) removing the sacrificial gate and the portion of the first layer (105) located above the sacrificial gate; e) depositing a third layer (119) of a two-dimensional semiconducting material; f) depositing a fourth layer (121) of an insulating material on the third layer (119); and g) forming a conductive gate (123) in the opening (117), on the fourth layer (121).