Self-Aligned Gate Nano FET with Segmented Electrodes
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Solution Overview
Problem
Current self-aligned gate structures for carbon nanotube FETs face challenges with high contact resistance due to thin source and drain electrodes, limited metal choices for gate electrodes, and inability to adjust threshold voltage, which hinders the development of high-performance nanoelectronic devices and integrated circuits.
Innovation Solution
A self-aligned gate structure is developed using one-dimensional semiconducting nanomaterials with a gate dielectric layer grown by ALD and a conductive gate electrode deposited by E-beam evaporation or magnetron sputtering, allowing for electrical separation from source and drain electrodes, using high work function metals for p-type and low work function metals for n-type FETs, and enabling flexible material choices for the gate dielectric and electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If thin source and drain electrodes are used to separate gate from source/drain, then parasitic capacitance is reduced, but contact resistance between source/drain electrodes and channel becomes very large
Solution Approach 1:
The source and drain electrodes are segmented into two parts: a thick bottom portion that contacts the channel to ensure low contact resistance, and a thin top portion that is separated from the gate electrode to reduce parasitic capacitance. This segmentation allows each part to optimize for its specific function.
Solution Approach 2:
Different thicknesses are applied to different parts of the source/drain electrodes. The bottom portion has greater thickness for low resistance contact, while the top portion has reduced thickness for capacitance reduction. This local variation in geometry optimizes both conflicting requirements.
2Ease of manufacture
If aluminum gate electrode is baked in air to form Al2O3 layer for separation, then self-aligned structure is achieved, but only low work function metals are suitable limiting threshold voltage adjustment
Solution Approach 1:
The gate structure is segmented into a bottom gate electrode portion for electrical separation and a top gate electrode portion for voltage control. This segmentation allows the bottom portion to be oxidized for separation while the top portion can use any metal for threshold voltage adjustment.
Solution Approach 2:
The oxide layer formed on the bottom gate electrode portion acts as an intermediary that provides both electrical separation and a platform for depositing the top gate electrode portion. This intermediary structure enables versatile material choices for the top gate.
3Ease of manufacture
If source and drain electrodes are made thin to achieve separation, then gate separation is improved, but device speed and performance are degraded due to high contact resistance
Solution Approach 1:
The source/drain electrodes are segmented vertically with a thick bottom portion for low resistance contact to the channel and a thin top portion for gate separation. This segmentation resolves the contradiction between contact quality and gate isolation.
Solution Approach 2:
The electrode thickness is optimized locally: thick at the channel interface for low resistance and thin at the gate interface for separation. This local quality variation maintains both good contact and effective gate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure reduces parasitic capacitance, enhances switch speed, and allows for adjustable threshold voltage, leading to improved performance and cost-effectiveness in nanoelectronic device fabrication.
Implementation Method 1
a gate dielectric layer grown by ALD
Implementation Method 2
a conductive gate electrode deposited by E-beam evaporation
Implementation Method 3
magnetron sputtering
Data Source
AI summary
Our invention discloses a self-aligned-gate structure for nano FET and its fabrication method. One dimension semiconductor material is used as conductive channel, whose two terminals are source and drain electrodes. Gate dielectric grown by ALD covers the area between source electrode and drain electrode, opposite sidewalls of source electrode and drain electrode, and part of upper source electrode and drain electrode. Gate electrode is deposited on gate dielectric by evaporation or sputtering. Total thickness of gate dielectric and electrode must less than source electrode or drain electrode. Gate electrode between source electrode and drain electrode is electrically separated from source and drain electrode by gate dielectric. The fabrication process of this self-aligned structure is simple, stable, and has high degree of freedom. Nearly the whole conductive channel between source electrode and drain electrode is covered by gate electrode, so the control efficiency of the gate over the conductive channel, described as transconductance, can be greatly enhanced. Additionally, there is no restriction on material of gate dielectric or electrode, so the devices' threshold voltage can be adjusted to satisfy the requirements of large scale integrated circuit.