Self-Aligned Gate Polysilicon Formation via Isolation Structure Masking
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Solution Overview
Problem
Conventional methods for manufacturing gate structures in integrated circuits face challenges such as misalignment in patterning, low device yields due to leakage, and inefficiencies in complex manufacturing processes, particularly at smaller technology nodes like 0.18 μm and below.
Innovation Solution
A method involving a semiconductor substrate with a pad oxide and silicon nitride layer, forming a trench region filled with oxide material using plasma deposition, planarizing, and selectively removing the silicon nitride to create an isolation structure, followed by depositing polysilicon and planarizing to form self-aligned gate structures, reducing the need for lithography and minimizing defects like polysilicon dishing and isolation erosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithography and etch processes are used for gate structure fabrication, then device geometry can be reduced, but manufacturing precision deteriorates due to misalignment and leakage
Solution Approach 1:
The patent applies preliminary action by forming the isolation structure before the gate structure fabrication. The silicon nitride layer is deposited and patterned first to create the isolation structure, which then serves as a self-aligned mask for subsequent polysilicon gate formation. This preliminary positioning eliminates the need for separate lithography alignment steps, resolving the misalignment issue while maintaining reduced device geometry.
Solution Approach 2:
The isolation structure serves a dual function: it acts as both the isolation element and the alignment reference for the gate structure. The self-aligned process uses the isolation structure's own position to define the gate location, making the system self-service in terms of alignment. This eliminates external lithography alignment requirements and prevents leakage issues associated with conventional multi-step alignment processes.
2Productivity
If complex manufacturing processes are used to achieve high device density, then circuit density improves, but device reliability deteriorates due to leakage and manufacturing defects
Solution Approach 1:
The patent merges the isolation structure formation and gate structure alignment into a single self-aligned process. The silicon nitride layer serves both as the isolation structure material and as the alignment reference for the polysilicon gate. This merging eliminates multiple separate lithography and etch steps, reducing manufacturing complexity while maintaining high device density and improving reliability by eliminating alignment-related leakage defects.
Solution Approach 2:
The patent extracts the alignment function from the conventional lithography process and integrates it into the isolation structure formation step. By taking out the separate alignment lithography step and using the isolation structure itself as the alignment reference, the process simplifies manufacturing while maintaining precision, thereby improving device yield without sacrificing density.
3Manufacturing precision
If multiple lithography steps are used for gate patterning, then manufacturing precision improves, but productivity deteriorates due to increased process steps and time
Solution Approach 1:
The patent performs the alignment reference creation as a preliminary action during isolation structure formation. The silicon nitride layer is deposited and patterned first, creating the alignment reference that will be used for gate formation. This preliminary positioning eliminates the need for subsequent alignment lithography steps, maintaining patterning precision while significantly improving process throughput by reducing the total number of steps.
Solution Approach 2:
The isolation structure serves itself as the alignment reference for gate formation, eliminating the need for external lithography alignment steps. This self-service approach maintains manufacturing precision because the alignment is defined by the physical structure itself rather than by separate photomask alignment, while simultaneously improving productivity by reducing process steps and cycle time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device yields and reduces process steps, achieving higher complexity and density with improved device reliability by eliminating misalignment and defects associated with conventional methods, and is compatible with existing equipment and processes.
Implementation Method 1
The method includes filling the trench region with an oxide material using a plasma deposition process
Data Source
AI summary
A method for processing semiconductor devices includes providing a semiconductor substrate. The method includes forming a pad oxide layer overlying the substrate and forming a silicon nitride layer overlying the pad oxide layer. The method includes forming a trench region extending through an entirety of a portion of the silicon nitride layer and extends into a depth of the semiconductor substrate. The method also includes filling the trench region with an oxide material. The oxide material extends from a bottom portion of the trench region to an upper surface of the silicon nitride layer. The method includes planarizing the oxide material and selectively removing the silicon nitride layer to form an isolation structure. A polysilicon material is deposited overlying the isolation structure. The polysilicon material is planarized to expose a top portion of the isolation structure and form a first electrode and a second electrode structures separated by a portion of the isolation structure.