Self-Aligned Gate Structure for High-Density Semiconductor Devices
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Solution Overview
Problem
The challenge in producing semiconductor devices with high integration density is the difficulty in suppressing leak currents due to the nano-scale dimensions of MOS transistors, which leads to issues with void formation between silicon pillars and non-self-aligned gate material processing.
Innovation Solution
A method involving the formation of planar and pillar-shaped silicon layers, followed by the deposition of oxide films and metal-polysilicon films, with anisotropic etching to create a self-aligned gate structure, using a metal gate and polysilicon film with a laminated structure, and forming silicides to reduce resistance and ensure insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between silicon pillars is decreased to increase integration density, then the degree of integration is improved, but voids are formed between the silicon pillars due to the need for thick gate material deposition
Solution Approach 1:
The patent transitions from planar gate material deposition to three-dimensional conformal deposition that uniformly coats the sidewalls of closely-spaced silicon pillars. By depositing gate material in a vertical dimension that conforms to the pillar surfaces, the method eliminates void formation between pillars while maintaining small pitch dimensions, thus resolving the contradiction between high integration density and manufacturing precision.
2Ease of manufacture
If a resist pattern covering the upper portion of silicon pillars is used to form gate lines, then gate line formation is achieved, but the process is not self-aligned and requires additional steps
Solution Approach 1:
The patent implements a self-aligned process where the gate line is automatically positioned using the silicon pillars themselves as alignment references. The conformal deposition and subsequent etching steps naturally form gate lines that are precisely aligned with the pillars without requiring separate resist patterning operations, thereby eliminating the need for covering resists and reducing process complexity.
Solution Approach 2:
The method performs preliminary conformal deposition of gate material on all surfaces of the silicon pillars before any gate line formation steps. This preliminary action creates a uniform gate structure that inherently defines the gate line position, eliminating the need for subsequent resist-based alignment operations and simplifying the overall manufacturing process.
3Reliability
If thick gate material is deposited between silicon pillars to maintain gate integrity, then gate material coverage is improved, but voids are formed and etching back creates holes in the gate material
Solution Approach 1:
The patent applies conformal deposition that provides uniform gate material thickness specifically on the sidewalls of each silicon pillar, rather than attempting to deposit a uniform thick layer across the entire inter-pillar space. This local quality approach ensures adequate gate coverage on critical surfaces while avoiding void formation in the spaces between pillars, thus resolving the contradiction between gate integrity and material uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a self-aligned process for producing semiconductor devices with a high degree of integration, reducing capacitance and ensuring reliable insulation between the gate line and substrate, while allowing for easy formation of silicides that connect diffusion layers, thus enhancing integration density and reducing resistance.
Implementation Method 1
forming an oxide film hard mask on the first pillar-shaped silicon layer and the second pillar-shaped silicon layer
Implementation Method 2
performing anisotropic etching to form the gate line
Implementation Method 3
forming silicides to reduce resistance and ensure insulation
Data Source
AI summary
In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.