Self-Aligned Metal Gate Separation for Dense Multigate ICs
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Solution Overview
Problem
Existing gate-all-around (GAA) devices face challenges in dense packing of IC features due to non-self-aligned gate cutting techniques, which can lead to damage to the gate structure and hinder the scaling of IC technologies.
Innovation Solution
A self-aligned metal gate cutting technique is developed, which forms separation structures between gate structures without damaging the gate, allowing for smaller spacing between active device areas and reducing the dimensions of metal gates, thereby increasing pattern density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-self-aligned gate cutting techniques are used to isolate gates of different GAA devices, then gate separation can be achieved, but the spacing between active device areas increases and gate structure damage may occur
Solution Approach 1:
The patent applies preliminary action by forming the gate separation structure before completing the gate electrode formation. Specifically, the dielectric material is deposited and patterned to create separation regions between adjacent GAA devices before the metal gate electrode is deposited. This preliminary formation of separation structures ensures that subsequent gate cutting processes do not damage the gate electrodes, as the separation structures are already in place to protect and define the gate boundaries.
Solution Approach 2:
The patent uses dielectric material as an intermediary substance to achieve gate separation. The dielectric material is deposited between adjacent gate structures and patterned to form isolation regions. This intermediary dielectric layer enables clean separation of gates without requiring direct mechanical cutting that could damage the gate electrodes, thus maintaining gate structure integrity while achieving the necessary isolation.
2Ease of manufacture
If non-self-aligned gate cutting techniques are used, then gate isolation can be achieved, but manufacturing complexity and risk of gate damage increase
Solution Approach 1:
The gate separation structure is formed preliminarily before gate electrode deposition. The dielectric material is deposited conformally and then patterned to create separation regions. This preliminary action simplifies the overall manufacturing process by establishing clear separation boundaries before the sensitive gate electrode formation, eliminating the need for complex post-gate-cutting alignment procedures and reducing the risk of gate damage.
Solution Approach 2:
The self-aligned nature of the process allows the gate separation structure to define its own boundaries automatically through conformal deposition on the fin structures. The dielectric material naturally conforms to the fin sidewalls and automatically positions the separation regions correctly without requiring additional alignment steps, thereby simplifying manufacturing while ensuring reliable gate isolation.
3Quantity of substance
If conventional gate cutting techniques are used, then device isolation can be achieved, but pattern density decreases
Solution Approach 1:
The patent transitions from planar gate cutting to three-dimensional self-aligned separation. By depositing dielectric material conformally on the vertical fin structures and using the fin geometry itself to define the separation regions, the process exploits the vertical dimension to achieve precise gate isolation. This dimensional approach allows tighter spacing between devices while maintaining proper isolation, thereby increasing pattern density without compromising device isolation.
Data Source
AI summary
Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.


