Self-Aligned Gate Trench Fabrication Using TTO Poly Spacer
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Solution Overview
Problem
Current methods for fabricating recessed-gate MOS transistors in DRAMs face challenges such as difficulty in controlling recess depth, threshold voltage control issues, and misalignment problems during polysilicon deposition and lithography processes, leading to short channel effects and increased bit line contact resistance.
Innovation Solution
A self-aligned method involving a semiconductor substrate with trench capacitors, an etching stop layer, masking spacer, and oxide spacer for forming a self-aligned gate trench, followed by deposition of gate dielectric and gate material layers to fill the trench, reducing the need for multiple polysilicon deposition steps and improving alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dry etching methods are used to form recesses, then the recess can be formed in the semiconductor substrate, but it is difficult to control the recess depth uniformly across the wafer
Solution Approach 1:
An etching stop layer is introduced as an intermediary between the semiconductor substrate and the etching process. This stop layer has a specific etching rate that allows precise control of the gate trench depth, ensuring uniform recess depth across the wafer while simplifying the etching control process.
Solution Approach 2:
The etching stop layer is deposited in advance before the gate trench etching process. This preliminary action establishes a predefined depth limit that ensures uniform recess depth across the wafer, eliminating the need for complex real-time etching control.
2Adaptability or versatility
If multiple polysilicon deposition steps and lithography processes are used to form gate structures, then the gate structure can be formed in both support circuit area and memory array area, but misalignment and shorting issues occur
Solution Approach 1:
The method uses self-aligned processes where the gate trench is formed using the trench top layer and masking spacer as alignment references. This self-service approach eliminates the need for separate lithography alignment steps, preventing misalignment and shorting issues while maintaining the ability to form gate structures in different areas.
Solution Approach 2:
The formation of gate trenches in both support circuit area and memory array area is merged into a single etching process using a unified masking scheme. This combines the previously separate processes into one step, improving alignment accuracy while maintaining versatility.
3Reliability
If the recess depth is increased to reduce short channel effects, then the effective channel length is lengthened, but the manufacturing precision and control become more difficult
Solution Approach 1:
The etching stop layer acts as a mediator that enables precise control of recess depth. By selecting materials with appropriate etching rate differences, the method achieves reliable suppression of short channel effects through controlled trench depth while maintaining manufacturing precision.
4Ease of manufacture
If conventional etching methods are used without self-alignment, then the gate trench can be formed, but misalignment increases bit line contact resistance
Solution Approach 1:
The gate trench formation process uses self-alignment where the trench top layer and masking spacer automatically define the trench position. This self-service mechanism ensures proper alignment without additional alignment steps, reducing bit line contact resistance while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances control over recess depth and reduces misalignment issues, improving the integrity of electrical isolation and consistent operation of DRAMs by forming a self-aligned gate trench, thereby addressing the limitations of existing recessed-gate technologies.
Implementation Method 1
oxidizing the masking spacer to form an oxide spacer
Implementation Method 2
dry etching the etching stop layer and the semiconductor substrate, thereby forming a self-aligned gate trench
Data Source
AI summary
A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.