Self-Aligned Gate Tunneling Transistor with Sublithographic Junction
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Solution Overview
Problem
Current tunneling effect transistors have a large footprint and high parasitic capacitance, making them unsuitable for practical integration due to low drive current per unit area and requiring complex processing steps, which limits their scalability and integration into standard CMOS processing.
Innovation Solution
The development of tunneling effect transistor structures with a self-aligned gate of sublithographic length, achieved through the formation of mandrels, dummy spacers, and precise ion implantation and annealing processes, allowing for the creation of p-n junctions aligned with the gate electrode and enabling compact size and high drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional lithographic means are used to form the gate, then the gate can be manufactured with standard processes, but the gate length is limited to lithographic dimensions resulting in larger device footprint
Solution Approach 1:
The patent forms dummy spacers around the gate structure before final gate patterning. These dummy spacers serve as preliminary structures that define the gate length to be sublithographic, allowing the gate to extend beyond what conventional lithography can directly pattern while maintaining manufacturing feasibility through subsequent etching processes.
Solution Approach 2:
The patent transitions from planar lithographic patterning to three-dimensional self-aligned patterning using dummy spacers. By adding the vertical dimension with spacer deposition and selective etching, the gate length can be controlled at sublithographic dimensions while the lithography step only needs to define the dummy spacer footprint, not the final gate length.
2Productivity
If the device footprint is reduced to increase drive current per unit area, then integration density improves, but parasitic capacitance increases due to closer spacing
Solution Approach 1:
The patent segments the gate structure into multiple components: the actual gate electrode, dummy spacers, and isolation structures. This segmentation allows the functional gate to be small for high drive current while dummy spacers and isolation regions are positioned to electrically isolate adjacent devices, reducing parasitic capacitance between neighboring transistors.
Solution Approach 2:
The patent introduces dummy spacers as intermediary structures between the gate and adjacent devices. These spacers act as electrical isolation barriers that reduce parasitic capacitance coupling between neighboring transistors, allowing devices to be placed closer together for higher integration density without excessive parasitic effects.
3Reliability
If epitaxial silicon deposition steps are used to create vertical tunneling structures, then tunneling effect is achieved, but processing complexity increases and integration into standard CMOS becomes difficult
Solution Approach 1:
The patent changes the material parameter from epitaxial silicon to silicon-germanium alloy for the dummy spacer and isolation structures. This material substitution enables selective etching processes that simplify manufacturing while maintaining the tunneling effect in the channel region, reducing processing complexity and enabling CMOS integration.
Solution Approach 2:
The patent extracts the tunneling function to only the channel region while using different materials (silicon-germanium) for the dummy spacers and isolation structures. This separation allows the tunneling effect to be maintained where needed while simplifying the overall processing by enabling selective removal and replacement of non-functional structures with standard CMOS-compatible materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a compact tunneling effect transistor with high drive current per unit area and reduced parasitic capacitance, facilitating integration into standard CMOS processing and enhancing scalability.
Implementation Method 1
A mandrel and an outer dummy spacer located thereupon are formed at a gate level on a semiconductor region
Implementation Method 2
Dopants of a first conductivity type are implanted into exposed portions of the semiconductor region to form a first conductivity type region
Implementation Method 3
An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion
Data Source
AI summary
In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.