Self-Aligned Conductive Features for Low-Resistance IC Contacts
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Solution Overview
Problem
As IC technology advances, the scaling down of multilayer interconnect features leads to increased contact resistance and misalignment issues, which hinder signal routing efficiency and pose performance, yield, and cost challenges.
Innovation Solution
A self-aligned interconnect architecture is developed, featuring metal lines and vias with a common composition to reduce contact resistance and misalignment, specifically designed for source/drain features, which includes forming contacts and vias that are self-aligned and share the same material composition to minimize overlay shifts and interface resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multilayer interconnect features are scaled down to increase functional density, then production efficiency is improved and costs are lowered, but contact resistance increases and misalignment occurs among conductive layers
Solution Approach 1:
The patent merges the contact and via formation processes into a single self-aligned operation. The contact is formed first, then the via is formed using the contact as an alignment reference, ensuring they share the same lateral position. This merging of formation steps eliminates misalignment between contacts and vias, reducing contact resistance while maintaining the benefits of scaled-down features for high functional density.
Solution Approach 2:
The contact structure serves as its own alignment reference for via formation. The via is formed using the contact's lateral position as the reference, making the system self-aligning. This self-service approach ensures that even as features are scaled down, the contact and via maintain precise alignment, preventing increased contact resistance that would normally occur at smaller dimensions.
2Ease of manufacture
If conventional interconnect structures are used, then manufacturing is simpler, but contact resistance is higher and signal routing efficiency is reduced
Solution Approach 1:
The patent merges the contact and via formation processes into a single self-aligned operation. The contact is formed first, then the via is formed using the contact as an alignment reference, ensuring they share the same lateral position. This merging of formation steps eliminates misalignment between contacts and vias, reducing contact resistance and improving signal routing efficiency while maintaining manufacturing simplicity through the integrated process.
Data Source
AI summary
A method of forming a semiconductor structure includes providing a semiconductor substrate having a source/drain feature and a gate structure formed thereon; forming an interlayer dielectric layer on the semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a dielectric liner on sidewalls of the trench; filling a metal layer in the trench; recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and refilling a dielectric material layer in the recess.