Self-Aligned Multi-Level IC Features Using Grayscale Lithography
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Solution Overview
Problem
The challenge in IC die fabrication is the misalignment between features in different levels of an IC structure, which is becoming increasingly difficult to manage with traditional alignment techniques.
Innovation Solution
The use of grayscale lithography processes with dose-dependent photoresists and iterative development to concurrently define via and line features, allowing for the transfer of heterogeneous features into different levels of an IC structure with no misalignment, achieved through a single exposure process and subsequent thin film etch or deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional alignment techniques are used to align features in different IC structure levels, then the alignment precision can be maintained within certain limits, but the misalignment between levels increases as scaling progresses, making feature alignment increasingly difficult
Solution Approach 1:
The patent merges the formation of via features and line features into a single grayscale lithography exposure process. By using dose-dependent photoresists and iterative development, both feature types are defined concurrently from one exposure, eliminating the need for separate alignment operations and thus resolving the misalignment problem inherent in traditional multi-step alignment techniques
Solution Approach 2:
The patent employs self-alignment mechanisms where the grayscale lithography process inherently aligns via and line features through dose-dependent photoresist development. The photoresist automatically differentiates between via regions (higher dose) and line regions (lower dose), creating self-aligned features without requiring external alignment apparatus or complex alignment procedures
2Manufacturing precision
If grayscale lithography with iterative development is used to concurrently define via and line features, then misalignment between levels is eliminated, but the process complexity and number of steps increase
Solution Approach 1:
The patent changes the exposure dose parameter across different regions of the photoresist to define different feature types. By varying the dose (higher for via regions, lower for line regions) within a single exposure, the process creates heterogeneous features with precise alignment. The iterative development process further refines this by selectively removing photoresist based on accumulated dose, transforming a complex multi-exposure process into a simplified single-exposure workflow
3Adaptability or versatility
If conventional multi-exposure processes are used to define different feature levels, then feature heterogeneity can be achieved, but alignment errors accumulate between exposures
Solution Approach 1:
The patent combines multiple exposure functions into a single grayscale lithography exposure. Instead of performing separate exposures for via features and line features (which would accumulate alignment errors), both feature types are defined simultaneously in one exposure using spatially varying dose. This merging eliminates alignment error accumulation while maintaining feature heterogeneity through dose-dependent photoresist response
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise alignment of via and line features without misalignment, reducing line end-to-end spacing and allowing for higher line density by ensuring exact alignment of via sidewalls with line sidewalls, thereby improving the fabrication process.
Implementation Method 1
grayscale lithography processes with dose-dependent photoresists
Data Source
AI summary
Patterning features within two levels of an integrated circuit (IC) structure with a grayscale lithography process. Via and line features may be defined concurrently into a resist having a dose dependent development response using a single mask exposure comprising two or more non-zero doses. The resist may be iteratively developed two or more times and an intervening thin film etch or deposition may be practiced to transfer mask features into the IC structure. The resulting via/line in first IC interconnect level may then have no misalignment with a via/line in a second IC interconnect level within each of two orthogonal dimensions of the IC structure.