Self-aligned IGBT with Deep p-type Column Structures
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Solution Overview
Problem
Current insulated gate bipolar transistor (IGBT) devices face challenges in reducing forward voltage drop, minimizing switching losses, and enhancing safe operation area while preventing latch-up and improving robustness, due to trade-offs between MOSFET resistance and carrier modulation.
Innovation Solution
The implementation of deep p-type column structures surrounding active MOSFET cell arrays, filled with p-poly silicon and featuring dielectric side wall spacers, which reduce spreading resistance and improve breakdown voltages, and the use of a novel high voltage termination structure with floating deep p-columns to prevent latch-up and enhance robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high levels of carrier modulation are used to reduce forward voltage drop, then Vce-Sat is improved, but safe operation area degrades
Solution Approach 1:
The patent creates localized high-doping regions in the column structure that provide low resistance paths during normal operation, while maintaining lower doping in the drift region to preserve carrier lifetime and SOA characteristics. This local quality differentiation resolves the contradiction between Vce-Sat and SOA.
2Loss of energy
If low MOSFET on-state resistance is used to reduce forward voltage drop, then Vce-Sat is improved, but latch-up resistance decreases and robustness worsens
Solution Approach 1:
The patent implements high doping concentration specifically in the column structure to reduce on-state resistance, while maintaining lower doping in the drift region to preserve latch-up resistance. This localized doping strategy resolves the contradiction between Vce-Sat and robustness.
Solution Approach 2:
The device is segmented into column structure and drift region with different doping optimization goals. The column structure is optimized for low resistance, while the drift region maintains characteristics for high latch-up resistance, resolving the contradiction between power loss and robustness.
3Loss of energy
If deeper junctions are formed to reduce spreading resistance, then Vce-Sat is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms the column structure with deep p-type doping before forming the drift region. This preliminary action creates the low-resistance path early in the process, simplifying subsequent manufacturing steps while achieving the desired deep junction characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces voltage drop, improves turn-off speed, and increases the safe operation area of IGBT devices, making them more robust and efficient for high voltage applications by minimizing switching losses and preventing latch-up.
Implementation Method 1
spreading resistance reduction
Implementation Method 2
dielectric side wall spacers formed on the trench side walls
Implementation Method 3
a deep region of the second conductivity extending from the bottom wall of the trench
Implementation Method 4
controlling carrier injection
Data Source
AI summary
A vertical IGBT device is disclosed. The vertical IGBT structure includes an active MOSFET cell array formed in an active region at a front side of a semiconductor substrate of a first conductivity type. One or more column structures of a second conductivity type concentrically surround the active MOSFET cell array. Each column structure includes a column trench and a deep column region. The deep column region is formed by implanting implants of the second conductivity type into the semiconductor substrate through the floor of the column trench. Dielectric side wall spacers are formed on the trench side walls except a bottom wall of the trench and the column trench is filled with poly silicon of the second conductivity type. One or more column structures are substantially deeper than the active MOSFET cell array.