Self-Aligned Inner Spacers for Uniform GAA Channel Length
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistors faces challenges in forming uniform inner-spacers, leading to non-uniformity and degradation of integrated chip performance due to misalignment and variability in channel length.
Innovation Solution
A self-aligned inner spacer formation method is devised, utilizing a treatment process to create etch selectivity between different parts of the inner spacer material, ensuring precise control over dimensions and positions, thereby enhancing channel length uniformity across nanosheets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional inner-spacer formation methods are used, then the fabrication process is simpler, but the inner-spacer alignment uniformity deteriorates leading to channel length variations
Solution Approach 1:
The method performs preliminary actions by forming a first sacrificial layer and first spacer before removing them to create recesses. This preliminary structure formation enables precise positioning of the second spacer material, ensuring uniform inner-spacer alignment while managing fabrication complexity through staged processing
Solution Approach 2:
The patent introduces intermediary elements including first and second sacrificial layers that mediate the formation process. These sacrificial layers serve as temporary structures that guide the precise placement of spacers, enabling controlled alignment without requiring direct complex positioning operations
2Reliability
If inner-spacer formation is performed to reduce capacitance and prevent leakage, then device performance is improved, but misalignment introduces non-uniformity degrading integrated chip performance
Solution Approach 1:
The method applies local quality by forming spacers with specific materials and properties in different locations. The first and second spacers are formed with different materials having different etch selectivities, allowing precise local control of inner-spacer formation to maintain uniformity while achieving the desired capacitance reduction and leakage prevention
Solution Approach 2:
The patent utilizes parameter changes through selective etching processes that exploit differences in etch selectivity between different spacer materials. By controlling etching parameters and using materials with distinct etch rates, the method achieves precise inner-spacer dimensional control and alignment uniformity, ensuring consistent device performance
3Productivity
If multi-gate devices are scaled down aggressively, then production efficiency increases and costs decrease, but gate control and short-channel effects become more challenging
Solution Approach 1:
The patent implements another dimension by transitioning to gate-all-around structures where the gate wraps around the channel in multiple dimensions (top, bottom, and sidewalls). This multi-dimensional gate configuration enhances gate control over the channel, allowing aggressive scaling while maintaining effective electrostatic control and mitigating short-channel effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves improved uniformity and control of inner spacer dimensions, mitigating channel length variations and enhancing the performance of GAA devices.
Implementation Method 1
utilizing a treatment process to create etch selectivity between different parts of the inner spacer material
Data Source
AI summary
A semiconductor device includes nanostructures vertically stacked over each other and above a substrate, a metal gate feature wrapping around each of the nanostructures, first and second gate sidewall spacers sandwiching the metal gate feature, an epitaxial feature abutting the nanostructures, and a dielectric layer interposing the epitaxial feature and the metal gate feature. A first sidewall of the dielectric layer facing the metal gate feature has a curvature surface in a cross-sectional view perpendicular to a top surface of the substrate and along a lengthwise direction of the nanostructures, and a middle portion of the curvature surface bends towards the epitaxial feature and away from the metal gate feature.