Self-Aligned Interconnection Elements for 3D Integrated Circuits
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Solution Overview
Problem
Current methods for producing interconnection elements in 3D integrated circuits face challenges in size, distribution, and misalignment issues between superimposed semiconductor layers, requiring complex structures that can lead to short circuits and degradation of transistor characteristics.
Innovation Solution
A method involving the formation of a self-aligned interconnection element using a lateral insulating zone composed of selectively etchable dielectric materials, which surrounds a block etched from a stack of layers, allowing for direct contact with the gate electrode without passing through an upper metal stage, thus maintaining insulation and avoiding short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a contact structure rises to a metallic level and extends horizontally to connect different levels, then interconnection between levels is achieved, but the structure becomes complex and misalignment issues arise between superimposed layers
Solution Approach 1:
The patent transitions from traditional horizontal interconnection (in the plane) to vertical interconnection (through the thickness dimension). The contact structure passes directly through the insulating layer from one level to another, eliminating the need for horizontal extension and multiple metal stages, thus simplifying the structure while maintaining reliability
Solution Approach 2:
The patent pre-forms the contact structure through the insulating layer before final metal deposition. The lateral insulating zone is created in advance to define the contact position, ensuring self-alignment and preventing misalignment issues between superimposed layers without requiring complex alignment procedures
2Productivity
If the contact structure passes through the insulating layer to reach lower levels, then interconnection is achieved, but misalignment between levels causes manufacturing difficulties
Solution Approach 1:
The lateral insulating zone serves a dual function: it provides electrical insulation and simultaneously defines the contact position through self-alignment. The zone is formed by lateral etching from the contact opening, automatically positioning itself relative to the contact structure without requiring additional alignment steps or masks
Solution Approach 2:
The contact structure is pre-formed through the insulating layer with the lateral insulating zone defined in advance. This preliminary structuring ensures that subsequent metal deposition and interconnection formation occur at the correct positions, eliminating misalignment issues between superimposed layers
3Productivity
If the interconnection element is placed close to the active area of transistors, then connectivity is improved, but the risk of short circuits and degradation of transistor characteristics increases
Solution Approach 1:
The lateral insulating zone acts as an intermediary element between the contact structure and the transistor active area. It provides a protective barrier that maintains electrical insulation while allowing the contact to be positioned close to the active area for improved connectivity, thus preventing short circuits and protecting transistor characteristics
Solution Approach 2:
The insulating zone is localized specifically around the contact structure where it interfaces with the transistor active area. This localized insulation provides targeted protection exactly where the risk of short circuits exists, while maintaining overall connectivity efficiency without adding global structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of efficient, self-aligned interconnection elements close to the active area of transistors without additional masks, maintaining insulation and preventing short circuits, thereby improving the connectivity and integrity of 3D integrated circuits.
Implementation Method 1
The lateral insulating zone comprises a first dielectric layer based on a first dielectric material and a second dielectric layer based on a second dielectric material able to be etched selectively with respect to the first dielectric material
Data Source
Figure 1~2
Figure 3A~3B
Figure 4A~4B
AI summary
Method for making connection elements between two different levels of components of a 3D integrated circuit comprising steps of: - forming a lateral insulating zone based on at least one given conductive zone (24) among several interconnection zones of a first level (N1) of components, the insulating zone extending around a semiconducting layer of a second level (N2) in which at least one transistor is suitable for being formed, - removing a first portion of the lateral insulating zone (60) so as to form a first hole revealing said given conductive zone, - depositing in the hole a conductive material so as to form a first electrical connection element between the second component and said given conductive zone (24).