Self-Aligned Interconnect Cap Structure for Stacked Device Alignment
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Solution Overview
Problem
The challenge in fabricating integrated circuit structures lies in connecting stacked devices with minimal misalignment and structural impediments, particularly when devices are densely packed, as existing methods face issues with via misalignment and area consumption in forming interconnects between top and bottom devices.
Innovation Solution
The solution involves forming an interconnect structure adjacent to a dielectric on a first wafer with a uniform amorphous semiconductor bonding layer, bonding it to a second wafer with a matching layer, converting the amorphous layer to a silicide or germanide, and aligning it with a self-aligned conductive cap structure to minimize misalignment and optimize connectivity between device levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via formation methods are used to connect stacked devices, then interconnect structures can be formed between device levels, but misalignment between top and bottom devices occurs and area consumption increases
Solution Approach 1:
The interconnect structure performs dual functions: it serves as the conductive pathway itself and simultaneously as the alignment reference feature for self-aligning subsequent vias. The via is formed to directly contact the interconnect structure, using the interconnect's position to define the via location, thereby eliminating separate alignment processes and reducing area consumption.
Solution Approach 2:
The interconnect structure is formed first between device levels before via formation, establishing a predetermined position that guides subsequent via placement. This preliminary positioning allows via alignment to be determined by the interconnect structure's location rather than requiring independent alignment processes.
2Productivity
If devices are densely packed to achieve high density scaling, then device integration density increases, but misalignment and structural impediments in interconnect formation worsen
Solution Approach 1:
The interconnect structure serves as both the conductive element and the alignment reference, allowing via placement to be automatically determined by the interconnect position. This self-aligning mechanism maintains precision even when devices are densely packed, as each via independently references its corresponding interconnect structure.
Solution Approach 2:
The approach changes the fundamental parameter of alignment from being process-dependent (lithography and etching alignment) to being structure-dependent (via position determined by interconnect position). This parameter change enables high density scaling while maintaining alignment precision through the physical relationship between via and interconnect structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures precise alignment and reduced area consumption by forming a self-aligned silicide or germanide cap structure, providing low resistance and efficient connectivity between stacked devices, thus overcoming misalignment and structural impediments in densely packed circuits.
Implementation Method 1
converting the amorphous layer to a silicide or germanide
Implementation Method 2
converting the amorphous layer to a silicide or germanide
Data Source
Figure 1
Figure 2
Figure 3A~4
AI summary
An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.