Self-Aligned Interconnect Structure for Overlay Shift and Capacitance
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in forming precise interconnect structures due to issues like overlay shift and increased capacitance, which affect the electrical performance and reliability of integrated circuits.
Innovation Solution
A method involving the formation of a blocking layer on specific mask sub-layers and an etch stop layer to accurately pattern dielectric layers, ensuring precise alignment and reducing capacitance by separating the etch stop layer from the conductive structures, thereby eliminating overlay shift and reducing RC time constants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional Damascene process is used for forming interconnect structures, then interconnect structures can be formed, but overlay shift occurs and manufacturing precision deteriorates
Solution Approach 1:
The patent applies preliminary action by forming the etch stop layer before patterning the dielectric layer. This etch stop layer serves as a reference structure that enables precise alignment during subsequent etching operations, preventing overlay shift that would otherwise occur in conventional Damascene processes. The etch stop layer is formed in advance to establish alignment references before the actual interconnect patterning takes place.
Solution Approach 2:
The patent introduces an etch stop layer as an intermediary structure between the substrate and the dielectric layer. This intermediary layer acts as a reference plane that mediates the alignment between different patterning steps, enabling precise overlay without directly participating in the final interconnect structure. The intermediary etch stop layer facilitates accurate alignment while being separate from the conductive interconnect features.
2Productivity
If dielectric layers are placed close to conductive structures, then interconnect density increases, but capacitance increases and electrical performance deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the dielectric structure into multiple layers separated by an etch stop layer. This segmentation creates distinct regions that can be independently optimized - the first dielectric layer can be positioned close to conductive structures for density, while the etch stop layer provides electrical separation to control capacitance. The segmented structure allows simultaneous achievement of high interconnect density and controlled electrical performance.
Solution Approach 2:
The etch stop layer serves as an intermediary dielectric barrier between the first dielectric layer and the second dielectric layer. This intermediary structure provides electrical isolation that reduces capacitance between adjacent conductive structures while still allowing the dielectric layers to be positioned in a dense configuration. The intermediary etch stop layer mediates between the competing requirements of density and electrical performance.
3Adaptability or versatility
If multiple patterning steps are performed, then complex interconnect patterns are formed, but process complexity increases and manufacturing precision decreases
Solution Approach 1:
The patent applies self-service by designing the etch stop layer to automatically serve as an alignment reference for subsequent patterning steps. The etch stop layer is formed with specific geometric features that inherently guide the alignment of overlying dielectric and conductive layers. This self-aligning mechanism eliminates the need for complex external alignment procedures, allowing complex patterns to be formed while maintaining high manufacturing precision through the structure's own geometric constraints.
Data Source
AI summary
A method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.