Self-Aligned Interconnect Structure With Barrier-Free Contacts
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Solution Overview
Problem
As IC technologies advance towards smaller nodes, the increased compactness of multilayer interconnect features leads to higher contact resistance, causing performance delays and yield issues due to increased resistance-capacitance (RC) delay, which existing interconnects fail to adequately address.
Innovation Solution
A barrier-free and self-aligned interconnect architecture is introduced, which eliminates contact barriers, expands contact area, and achieves self-alignment between Mx and Vx layers, reducing contact resistance and capacitance, thereby improving reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multilayer interconnect features are made more compact to increase functional density, then the number of interconnected devices per chip area increases, but contact resistance increases causing performance delays
Solution Approach 1:
The patent merges the mandrel structure with the final interconnect structure by using the same patterned features as both the deposition template and the final conductive path. The mandrel is formed conformally on the substrate, patterned to define the interconnect geometry, and then remains as part of the final structure after copper deposition and mandrel removal, eliminating the need for separate alignment processes between via and trench patterns.
Solution Approach 2:
The mandrel structure serves multiple functions automatically: it defines the pattern for copper deposition, provides the geometric template for via and trench formation, and self-aligns subsequent layers without requiring additional photolithography alignment steps. The single patterning process inherently aligns all interconnect features.
2Ease of manufacture
If conventional interconnect structures with contact barriers are used, then manufacturing process is established, but contact resistance and capacitance increase reducing speed
Solution Approach 1:
The patent extracts and removes the contact barrier layer from the interconnect structure. By eliminating the barrier layer that normally prevents copper diffusion, the structure achieves lower contact resistance and capacitance. The mandrel-based self-aligned process inherently prevents copper diffusion without requiring a separate barrier layer, allowing direct copper deposition on the mandrel surface.
3Manufacturing precision
If alignment processes are added to reduce misalignment between via and trench patterns, then manufacturing precision improves, but device complexity and process steps increase
Solution Approach 1:
The patent combines multiple patterning steps into a single mandrel formation and patterning process. The mandrel is formed conformally and then patterned in one sequence, which simultaneously defines the geometry for all subsequent via and trench formations. This eliminates the need for separate alignment processes between different interconnect layers.
Solution Approach 2:
The interconnect formation process is segmented into distinct functional stages: mandrel conformal deposition, single patterning step, copper deposition, and mandrel removal. This segmentation allows each stage to be optimized independently while maintaining overall process simplicity and alignment precision.
Data Source
AI summary
The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.