Self-Aligned Interconnect Gratings for Sub-10 nm Alignment
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Solution Overview
Problem
Conventional lithographic methods face challenges in achieving precise alignment for high-density, high-performance transistor fabrication, leading to misalignment issues and increased electrical resistance as transistors are scaled below 10 nm, which affects the spacing and connectivity between transistors and peripheral circuitry.
Innovation Solution
The integration of directed self-assembly and damascene methods to form self-aligned integrated circuit interconnect structures, enabling precise alignment and control over the shape and size of metal lines and conductive vias, thereby mitigating misalignment and optimizing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic methods are used for transistor fabrication, then manufacturing process simplicity is maintained, but alignment precision deteriorates leading to misalignment between interconnect elements
Solution Approach 1:
The patent employs self-aligned fabrication processes where structures automatically position themselves relative to each other without requiring additional alignment steps. The self-aligned grating structures and interconnect elements form through processes that inherently maintain precise spatial relationships, eliminating the need for complex external alignment procedures while achieving sub-10nm precision.
Solution Approach 2:
The fabrication process is divided into distinct self-aligned stages where each stage produces structures that serve as alignment references for subsequent stages. The interconnect structure is segmented into grating layers, via holes, and fill structures that are formed sequentially with each layer automatically aligned to the previous ones through the self-aligned process.
2Productivity
If transistor size is reduced below 10 nm to increase density, then productivity is improved, but alignment precision deteriorates due to conventional lithographic limitations
Solution Approach 1:
The patent transitions from planar lithographic patterning to three-dimensional self-aligned grating structures. By forming vertical grating layers and via holes that extend through multiple levels, the process achieves precise alignment in the lateral dimension while accommodating reduced feature sizes through vertical stacking, thereby increasing transistor density without sacrificing alignment precision.
Solution Approach 2:
The fabrication process utilizes changes in material properties and process parameters at each self-aligned stage to achieve precise patterning at reduced dimensions. The grating structures, via hole formation, and fill processes employ controlled deposition and etching parameters that maintain precision even as feature sizes scale below 10 nm, enabling higher density while preserving alignment accuracy.
3Manufacturing precision
If self-aligned methods are used to improve alignment precision, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the self-aligned grating structures, which simultaneously serve as alignment references, conductive interconnects, and structural support elements. The via holes and fill structures are integrated into the same self-aligned process sequence, reducing the need for separate alignment procedures and simplifying the overall fabrication workflow despite the three-dimensional complexity of the resulting structure.
Data Source
AI summary
An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.