Self-Aligned Interconnect Formation via Multi-Mask Patterning
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Solution Overview
Problem
As semiconductor devices shrink, traditional photolithographic, etching, and deposition techniques face challenges in forming small, efficient interconnects with reduced defects, particularly due to overlay shift issues during lithography, leading to via-induced-metal-bridge and via-to-via leakage defects, and affecting time-dependent dielectric breakdown (TDDB) reliability.
Innovation Solution
A self-aligned process is employed to form interconnects with reduced size and pitch, using multiple mask layers and patterning processes to align conductive vias and lines accurately, avoiding optical proximity effects and enhancing dielectric layer patterning to improve interconnect reliability and reduce defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithographic techniques are used to form interconnects, then the manufacturing process is simpler, but overlay shift causes alignment errors leading to via-induced-metal-bridge and via-to-via leakage defects
Solution Approach 1:
The patent applies preliminary action by forming mandrels and sacrificial structures before the final interconnect pattern. The self-aligned via process uses pre-formed mandrels to define via locations, ensuring precise alignment without requiring high-precision overlay during subsequent lithography steps. This preliminary structuring eliminates alignment errors while maintaining process feasibility.
Solution Approach 2:
The patent introduces intermediary structures (mandrels, sacrificial layers, and spacers) that mediate between the lithography process and the final interconnect pattern. These intermediaries serve as alignment references and physical guides, transferring the pattern from the lithographic step to the etching step with high fidelity, thereby eliminating overlay shift issues.
2Area of moving object
If device size is reduced to improve integration density, then more devices fit on the substrate, but traditional techniques cannot form small interconnects with reduced defects
Solution Approach 1:
The patent implements self-service through self-aligned processes where the structure itself defines its own pattern. The mandrels and sacrificial structures automatically position the via openings and interconnect features without requiring external alignment references. This self-positioning mechanism maintains high pattern precision even at reduced feature sizes, eliminating the scaling limitations of traditional techniques.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional self-aligned structuring. By using vertical mandrels, sacrificial layers, and spacer formation, the process adds a dimensional aspect that enables precise lateral positioning through vertical structure collapse or spacer deposition, achieving high precision at small feature sizes.
3Manufacturing precision
If multiple photolithographic steps are used to achieve precise alignment, then alignment accuracy improves, but the number of process steps increases leading to higher complexity and cost
Solution Approach 1:
The patent merges multiple patterning functions into a single self-aligned process sequence. The mandrel formation, spacer deposition, and via etching are combined into one integrated flow where each step automatically positions the next feature. This consolidation maintains high alignment accuracy while reducing the total number of separate lithography and etching steps, thereby improving manufacturing efficiency.
4Reliability
If conventional etching and deposition techniques are used, then the process is well-established, but they cannot form small, efficient interconnects with reduced defects
Solution Approach 1:
The patent replaces conventional mechanical alignment systems with a self-aligned chemical and physical process. Instead of relying on mechanical overlay alignment between separate lithography steps, the process uses chemical vapor deposition for spacer formation and controlled etching that follows the mandrel geometry. This substitution eliminates mechanical alignment errors while using well-established deposition and etching techniques, maintaining reliability without excessive complexity.
Data Source
AI summary
A method includes forming a dielectric layer over a conductive feature. A first mask having a first opening is formed over the dielectric layer. A second mask is formed over the first mask. A third mask having a second opening is formed over the second mask. A fourth mask having a third opening is formed over the third mask, a portion of the third opening overlapping with the second opening. The portion of the third opening is transferred to the second mask to form a fourth opening, a portion of the fourth opening overlapping with the first opening. The portion of the fourth opening is transferred to the dielectric layer to form a fifth opening. The fifth opening is extended into the dielectric layer to form an extended fifth opening, the extended fifth opening exposing the conductive feature. The extended fifth opening is filled with a conductive material.