Self-Aligned Interconnect Structure for Low-Resistance IC Routing

The patent transitions from planar 2D interconnect layouts to 3D vertically stacked interconnect structures. Multiple interconnect layers are stacked vertically with vias connecting different levels, enabling signals to route through the third dimension. This reduces lateral congestion and allows continued scaling of lateral dimensions while maintaining signal routing efficiency.

The patent implements nested interconnect structures where smaller critical dimension features are positioned within or alongside larger features. Conductive plugs are nested within via holes, which are themselves nested within larger interconnect trenches. This nesting allows maximization of conductive material within available space, reducing resistance without increasing lateral footprint.

The patent employs composite interconnect structures with multiple materials having different properties. Copper or cobalt conductive plugs are combined with tungsten barrier layers, which are combined with dielectric materials. This multi-material approach allows optimization of each component: copper for low resistance, tungsten for mechanical strength and barrier properties, and dielectric for insulation, collectively reducing contact resistance despite smaller dimensions.

The patent applies different materials and structures to different regions of the interconnect system. High-conductivity copper plugs are used specifically at contact points where low contact resistance is critical, while tungsten barriers are applied locally at interfaces to prevent diffusion. This localized optimization addresses contact resistance issues without requiring uniform changes throughout the entire interconnect structure.

The patent performs preliminary patterning and alignment actions in earlier process steps. Hard mask layers are deposited and patterned before trench etching, establishing precise alignment references. Via holes are formed through selective etching using these pre-established masks, ensuring accurate positioning. This preliminary structuring creates self-aligning features that guide subsequent manufacturing steps, maintaining precision despite process complexity.

The patent introduces intermediary layers such as hard masks and spacer materials that facilitate precise alignment between different conductive layers. These intermediary structures act as templates or guides during etching and deposition processes, ensuring that vias align with underlying plugs and that upper interconnect lines align with lower layers. The intermediary elements absorb alignment tolerances and transfer precise positioning through multiple manufacturing steps.