Self-Aligned Interconnect Structure for Low-Parasitic Semiconductor Vias
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Solution Overview
Problem
The increasing complexity of interconnect structures in semiconductor devices due to rising transistor density leads to issues such as increased parasitic capacitance, resistance, and manufacturing errors, which negatively impact device performance and reliability.
Innovation Solution
The implementation of a self-aligned interconnect structure (SIS) that allows for the manufacture of semiconductor devices using a single manufacturing flow, reducing manufacturing complexity and eliminating the need for separate flows for top-to-bottom and bottom-to-top vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional separate manufacturing flows are used for top-to-bottom and bottom-to-top vias, then manufacturing precision can be maintained for each flow, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent merges the separate top-to-bottom and bottom-to-top via manufacturing flows into a single unified self-aligned interconnect structure manufacturing process. This is achieved by forming both types of vias simultaneously using the same alignment reference, eliminating the need for separate manufacturing flows while maintaining alignment precision through the self-aligned approach where vias are positioned relative to existing interconnect features rather than requiring independent alignment processes
2Object-affected harmful factors
If conductor width is reduced to decrease parasitic capacitance, then signal integrity improves, but resistance increases
Solution Approach 1:
The patent addresses the resistance-capacitance tradeoff by transitioning from planar interconnect geometry to a three-dimensional self-aligned interconnect structure. This vertical dimensionality change allows for optimized current paths and reduced parasitic effects without simply scaling conductor width, thereby managing both resistance and capacitance through spatial reconfiguration rather than dimensional reduction alone
3Productivity
If transistor area is reduced to increase density, then device integration improves, but interconnect crowding and parasitic capacitance increase
Solution Approach 1:
The patent resolves the interconnect crowding issue caused by high transistor density by utilizing three-dimensional self-aligned interconnect structures. This vertical stacking approach allows multiple interconnect layers to be formed in close proximity without increasing lateral crowding, thereby maintaining low parasitic capacitance even as transistor density increases in the planar dimension
Data Source
AI summary
A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.