Self-Aligned Interconnect Structure via Spacer Deposition
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Solution Overview
Problem
Conventional lithographic techniques face limitations in accurately forming vias with extremely small pitches and small opening sizes, leading to misalignment and shorts in semiconductor device interconnects, which hinders further miniaturization and increases costs.
Innovation Solution
A method involving the deposition of spacers and conformal metal layers on low-k dielectric layers, followed by etching and dielectric filling, to form self-aligned interconnect structures with vias having pitches as small as 20-30 nanometers, ensuring precise alignment and reducing shorts between adjacent metal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic techniques are used to form vias with small opening sizes and small pitches, then manufacturing simplicity is maintained, but manufacturing precision deteriorates leading to misalignment and defects
Solution Approach 1:
The fabrication process is divided into multiple sequential steps: forming mandrels with initial pattern, depositing spacers on mandrel sidewalls, removing mandrels, and repeating the process. This segmentation allows each step to be optimized independently, achieving 20-30nm pitch precision that cannot be achieved in a single lithographic step.
Solution Approach 2:
Mandrels are formed in advance as sacrificial structures that define the precise locations where vias will eventually be formed. The spacers are deposited preliminarily on mandrel sidewalls to establish the exact via positions before the mandrels are removed, ensuring self-alignment without requiring high-precision lithography at the final via dimensions.
2Productivity
If via opening size and pitch are reduced to increase device density, then productivity and miniaturization are improved, but manufacturing precision deteriorates due to lithography limits
Solution Approach 1:
Spacers serve as intermediary structures that transfer the pattern from mandrels to the final via locations. The spacers are deposited conformally on mandrel sidewalls, automatically positioning themselves with precise thickness control. This intermediary step bypasses the lithography resolution limit, enabling 20-30nm pitch via formation with high accuracy.
Solution Approach 2:
The patent replaces reliance on lithographic resolution (optical/mechanical system) with atomic layer deposition (chemical vapor deposition system) for defining via positions. The ALD process deposits spacers with atomic-level thickness control, achieving precision that cannot be obtained through conventional optical lithography at such small dimensions.
3Manufacturing precision
If multi-patterning processes are used to achieve small pitch vias, then manufacturing precision is improved, but device complexity increases due to additional process steps
Solution Approach 1:
The spacer deposition process is self-aligning by default, as spacers automatically form on the sidewalls of existing mandrels. This self-service mechanism eliminates the need for additional alignment steps and lithographic patterning, reducing process complexity compared to other multi-patterning techniques that require multiple litho-etch cycles with alignment requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-density, self-aligned interconnects with excellent gap fill and interface characteristics, reducing resistivity and eliminating shorts, thus facilitating further miniaturization and cost reduction in semiconductor manufacturing.
Implementation Method 1
depositing a plurality of spacers atop a top surface of a low-k dielectric layer including a plurality of recessed vias
Implementation Method 2
depositing a conformal metal layer atop the top surface of the low-k dielectric layer, the plurality of spacers, and within the one or more partially filled recessed vias
Implementation Method 3
etching the conformal metal layer to remove portions thereof to expose a top surface of the plurality of spacers, the top surface of the low-k dielectric layer between the plurality of spacers, and within the plurality of filled vias
Implementation Method 4
filling between the plurality spacers and within the second plurality of partially filled recessed vias with a dielectric material to form a second plurality of filled vias
Data Source
AI summary
Methods and apparatus for forming an interconnect structure, including: depositing a plurality of spacers atop a low-k dielectric layer including a plurality of recessed vias, wherein one or more of the plurality of spacers is deposited atop the top surface of the low-k dielectric layer and within one or more of the plurality of recessed vias to form a one or more partially filled recessed vias; depositing a conformal metal layer atop the low-k dielectric layer, plurality of spacers, and within the one or more partially filled recessed vias to form a plurality of filled vias; etching the conformal metal layer to remove portions thereof to form a second plurality of partially filled recessed vias; and filling between the plurality spacers and within the second plurality of partially filled recessed vias with a dielectric material to form a second plurality of filled vias.