Self-Aligned Interconnect Via Formation for Nanoscale Metal Lines
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Solution Overview
Problem
Traditional lithography and etch processes struggle to ensure acceptable alignment between interconnect vias and underlying conductive lines in multi-level interconnect structures, especially at nanoscale dimensions, due to limitations in hardmask material selection and processing.
Innovation Solution
A method for producing nano-sized interconnect vias involves forming a conductive layer and dielectric layer on a substrate, creating openings in the dielectric layer, filling them with conductive material, and planarizing the surface. Hardmask lines are then formed overlapping the vias, and the dielectric and conductive materials are removed except where covered by the hardmask, aligning the via with the conductive line and removing the hardmask and upper dielectric to create a planar surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional lithography and etch processes are used to form interconnect vias, then the process is simple and well-established, but alignment between vias and underlying conductive lines deteriorates at nanoscale dimensions
Solution Approach 1:
The hardmask lines are formed in advance and maintained on the metal lines during subsequent processing steps. These pre-positioned hardmask lines serve as alignment references that guide the via formation process, ensuring precise alignment between vias and underlying conductive lines before the actual via etching occurs.
Solution Approach 2:
The hardmask lines automatically define the via locations and dimensions through their own presence and geometry. The via openings are formed by removing hardmask material at specific locations, making the hardmask structure itself the template for via formation, thereby achieving self-alignment without requiring additional alignment steps.
2Manufacturing precision
If hardmask material is used for via alignment, then alignment precision is improved, but hardmask material remains after via formation increasing interlayer capacitance
Solution Approach 1:
The hardmask material is selectively removed from areas where it is no longer needed for alignment. After the via formation process is complete, the hardmask lines are stripped away, extracting the alignment reference function while eliminating the source of increased interlayer capacitance. This selective removal ensures that only the necessary minimum amount of hardmask material remains during critical processing steps.
Solution Approach 2:
The hardmask material is strategically positioned only where alignment is required - specifically on the metal lines at via locations. The hardmask is not uniformly applied across the entire surface but is locally placed to provide alignment references only where needed, minimizing its presence and associated capacitance effects in non-critical areas.
3Object-generated harmful factors
If hardmask material with low relative permittivity is used, then interlayer capacitance is reduced, but etch selectivity deteriorates
Solution Approach 1:
The etch process parameters are optimized and adjusted to achieve sufficient selectivity between the low-permittivity hardmask material and surrounding materials. By modifying etch chemistry, temperature, pressure, and other process parameters, the etch selectivity is enhanced despite using materials with lower permittivity, thereby resolving the trade-off between capacitance reduction and etch selectivity.
Data Source
AI summary
Methods and systems for producing an interconnect via are provided. A conductive layer is produced on a substrate having an upper surface of a dielectric material with conductors or contacts embedded in the dielectric material. A dielectric layer is produced on the conductive layer. An opening is formed in the dielectric layer and filled with a conductive material to form a conductive via. The dielectric layer and the via are planarized to a common planar level. At least one hardmask line which overlaps the via is formed. The dielectric material and the conductive material of the via and of the conductive layer are removed in the areas not covered by the hardmask line, resulting in a conductive line having an interconnect via on its top surface. The interconnect via is aligned to the width of the conductive line. The hardmask line is removed and a planar dielectric surface is produced.