Self-Aligned Interconnect Structure for Via Overlay Errors
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Solution Overview
Problem
As semiconductor technology advances, the challenge of accurately aligning vias with metal lines becomes increasingly difficult due to decreasing trench sizes, leading to misalignment and over-etching issues, which can result in poor device performance and reliability.
Innovation Solution
The method involves forming a capping layer over a metal layer, patterning it to create trenches, and then depositing a dielectric layer that protrudes from the metal layer to prevent over-etching, allowing for self-aligned via formation and the creation of air gaps between metal lines, which reduces the RC time constant and improves device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via formation processes are used, then manufacturing simplicity is maintained, but alignment precision deteriorates due to overlay errors
Solution Approach 1:
The dielectric layer is deposited and protrudes from the metal layer surface before via etching begins. This preliminary protrusion structure serves as a built-in alignment reference and physical barrier that prevents over-etching, thereby improving via alignment precision without requiring additional alignment steps during the via formation process.
Solution Approach 2:
The protruding dielectric layer automatically performs multiple functions: it provides alignment reference, prevents over-etching, and defines via depth. This self-service mechanism eliminates the need for external control mechanisms or additional process steps to ensure proper via alignment and depth control.
2Productivity
If trench sizes are decreased to increase functional density, then productivity is improved, but manufacturing precision deteriorates due to tighter process windows
Solution Approach 1:
The solution moves the alignment control from the planar dimension (2D overlay alignment) to the vertical dimension (3D protrusion height). By creating a dielectric protrusion that extends vertically from the metal layer, the alignment reference is established in the Z-direction, which is more robust against lateral overlay errors that plague scaled-down 2D processes.
Solution Approach 2:
The protruding dielectric structure is formed in advance before via etching, establishing alignment references and physical boundaries that guide subsequent via formation. This preliminary structure compensates for the reduced process margins inherent in smaller trench sizes.
3Reliability
If standard dielectric deposition is used, then manufacturing simplicity is maintained, but harmful factors increase due to over-etching and tiger tooth via formation
Solution Approach 1:
The protruding dielectric layer acts as a cushioning barrier deposited beforehand that physically prevents the etch front from penetrating too deeply into the underlying structure. This cushioning effect eliminates tiger tooth via formation and over-etching issues by providing a sacrificial material layer that absorbs etching variability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enlarges the process window for via formation, reduces the risk of 'tiger tooth' via formation, and enhances the reliability and performance of semiconductor devices by improving alignment and conductivity.
Implementation Method 1
depositing a dielectric layer that protrudes from the metal layer to prevent over-etching
Implementation Method 2
creation of air gaps between metal lines, which reduces the RC time constant
Data Source
AI summary
The present disclosure provides an exemplary semiconductor structure that includes a substrate having a conductive feature disposed in a top portion of the substrate, a metal line above the substrate and in electrical coupling with the conductive feature, a dielectric feature disposed on a sidewall of the metal line, an etch stop layer disposed on the dielectric feature and the meta line, and a via extending through the etch stop layer and in physical contact with top surfaces of the dielectric feature and the metal line. The metal line has a first metal, and the via has a second metal different from the first metal. The top surface of the dielectric feature is higher than the top surface of the metal line.