Self-Aligned Interconnect Via Using Ruthenium
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Solution Overview
Problem
Conventional methods for fabricating interconnect structures in semiconductor devices face challenges with misalignment and process complexity due to the use of copper, which results in poor adherence to dielectric materials, electro-migration, and the need for additional barrier layers, complicating integration and affecting electrical performance.
Innovation Solution
A method is developed to fabricate self-aligned interconnect structures using conductive materials like ruthenium (Ru) and cobalt (Co), which do not require diffusion barrier layers and have lower electrical resistance, with a process that aligns via openings over conductive lines and fills them with conductive materials that can be easily patterned using plasma etching and planarized using CMP, allowing for improved alignment and reduced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If copper is used as interconnect material, then interconnect propagation delay is reduced and interconnect density is enhanced, but adherence to dielectric materials is poor and electro-migration occurs requiring additional barrier layers
Solution Approach 1:
The patent changes the material parameter from copper to ruthenium, which has different physical and chemical properties including better adherence to dielectric materials and resistance to electro-migration, while maintaining acceptable electrical conductivity for interconnect applications
Solution Approach 2:
The patent employs a composite structure where ruthenium serves as the primary conductive material in the interconnect line, potentially combined with other materials to optimize both electrical performance and reliability characteristics
2Reliability
If diffusion barrier layers are added to copper interconnects, then electro-migration is prevented, but process integration becomes more complicated and resistance increases
Solution Approach 1:
The patent extracts and removes the diffusion barrier layer from the interconnect structure by using ruthenium, which inherently resists electro-migration and does not require a separate barrier layer, thereby simplifying the process integration
Solution Approach 2:
The patent eliminates the need for additional barrier layer materials and processing steps, reducing both material complexity and process steps in the interconnect fabrication sequence
3Ease of manufacture
If single damascene integration scheme is used, then process is simpler, but interconnect via and conductive line cannot be self-aligned
Solution Approach 1:
The patent inverts the conventional single damascene sequence by first forming the conductive line and then forming the via through the conductive line, which enables self-alignment while maintaining process simplicity
Solution Approach 2:
The patent performs preliminary formation of the conductive line before creating the via opening, establishing a reference structure that enables automatic self-alignment of subsequent via formation without requiring additional alignment steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-performance interconnect structures with improved alignment, reduced defects, and lower electrical resistance, overcoming the limitations of copper-based interconnects by eliminating the need for diffusion barrier layers and enhancing the reliability and speed of semiconductor devices.
Implementation Method 1
The via opening is filled with a conductive material to form an interconnect via
Implementation Method 2
The via opening is filled with a conductive material to form an interconnect via
Implementation Method 3
The conductive line is formed from a layer of conductive material that is etched using conventional plasma etching process
Implementation Method 4
The surface of the conductive line is subsequently planarized using conventional chemical mechanical planarization (CMP) process
Data Source
AI summary
A method of fabricating an interconnect structure of a semiconductor device is provided having a first conductive line and forming a second conductive line over the first conductive line. A via opening is formed in the second conductive line, and the via opening is aligned over the first conductive line. The via opening is filled with a conductive material to form an interconnect via and an upper portion of the interconnect via forms a portion of the second conductive line.