Self-Aligned Interconnect Deposition for Sub-50 Nm Vias
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Solution Overview
Problem
Conventional dual-damascene fabrication techniques face challenges with gap fill and resistivity constraints for feature sizes below 50 nm pitch, making it impractical for forming interconnect structures with low line and via resistance.
Innovation Solution
A method involving physical vapor deposition of an etch stop layer and a metal layer under vacuum conditions without air exposure, using a subtractive process to form aligned vias and contacts, with integrated deposition chambers for low resistivity films and self-aligned via formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dual-damascene fabrication techniques are used, then vias can be self-aligned with metal lines, but gap fill and resistivity constraints make it impractical for feature sizes below 50 nm pitch
Solution Approach 1:
The patent inverts the conventional dual-damascene approach by using a subtractive process instead of additive. Instead of filling trenches with conductive material, the method deposits metal layers conformally and then selectively removes portions through etching, achieving via formation through material removal rather than deposition and filling.
Solution Approach 2:
The patent changes the fundamental process parameters by transitioning from chemical vapor deposition and electroplating (dual-damascene) to physical vapor deposition methods. This parameter change enables better control at sub-50nm dimensions while maintaining via self-alignment through the conformal deposition process.
2Reliability
If conventional dual-damascene methods are used, then the process is well-established, but line resistance and via resistance are higher
Solution Approach 1:
The patent replaces the chemical-based dual-damascene process with a physical vapor deposition-based subtractive process. This substitution enables lower resistance interconnects by achieving better metal fill and reduced void formation, while the conformal deposition maintains process control and reliability.
Solution Approach 2:
The patent performs preliminary conformal metal deposition across the entire surface before selective removal. This preliminary action ensures uniform metal distribution and adhesion, preventing gaps and reducing resistance, while the subsequent selective etching creates the via structures with optimal metal fill.
3Area of moving object
If features are scaled to smaller dimensions below 50 nm pitch, then device density increases, but gap fill and resistivity constraints become more severe
Solution Approach 1:
The patent changes the deposition parameters by using physical vapor deposition methods that provide better step coverage and conformal deposition at sub-50nm dimensions. This parameter change eliminates gap fill issues that plague conventional methods at small dimensions while achieving the required feature sizes for high density.
Solution Approach 2:
The patent inverts the approach by using subtractive processing instead of additive filling. This inversion avoids the fundamental gap fill problems that occur when trying to deposit material into high-aspect-ratio trenches at sub-50nm dimensions, as the metal is deposited conformally and then selectively removed rather than attempted to be forced into narrow gaps.
4Object-affected harmful factors
If metal layers are deposited under vacuum conditions without air exposure, then metal oxidation is prevented and resistivity is reduced, but process complexity increases
Solution Approach 1:
The patent uses vacuum conditions as an inert environment to prevent metal oxidation during deposition. By maintaining vacuum throughout the process, the metal layers are protected from atmospheric oxygen, ensuring low resistivity without requiring additional protective atmosphere steps, thus managing complexity while achieving the desired protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces line resistance by 15-50% and via resistance by 20-30% compared to conventional dual-damascene methods, while maintaining low resistivity and preventing metal oxidation, enabling effective interconnect structure formation at smaller feature sizes.
Implementation Method 1
depositing an etch stop layer on a substrate, wherein deposition comprises physical vapor deposition
Implementation Method 2
in situ depositing a metal layer on the etch stop layer, wherein the in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma
Implementation Method 3
the in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer
Implementation Method 4
wherein the substrate is continuously under vacuum and is not exposed to ambient air
Data Source
AI summary
A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.