Self-Aligned Interconnection Structure With Lower Capacitance
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Solution Overview
Problem
The semiconductor industry faces challenges with reliability and high resistance in self-aligned contact (SAC) processes due to issues like high capacitance and misalignment during the manufacturing of conductive layers on substrates, particularly as feature sizes decrease and integration density increases.
Innovation Solution
A method for forming self-aligned interconnection structures without using self-assembled monolayers (SAMs), involving H2 plasma pre-treatment and the use of dielectric materials with ordered pores, which reduces the need for etch stop layers and minimizes capacitance and resistance by enabling direct contact between dielectric layers and improving selective deposition alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-assembled monolayers (SAMs) are used in self-aligned contact processes, then alignment accuracy is improved, but reliability deteriorates due to SAM-related issues
Solution Approach 1:
The patent removes self-assembled monolayers (SAMs) from the self-aligned contact process while maintaining alignment accuracy through alternative methods such as direct plasma treatment and optimized etch stop layer design, thereby eliminating SAM-related reliability issues
Solution Approach 2:
The patent introduces H2 plasma pre-treatment as an intermediary step to achieve the alignment and surface preparation functions previously provided by SAMs, eliminating the need for problematic monolayer formation
2Manufacturing precision
If etch stop layers with high dielectric constant are used, then manufacturing precision is improved, but capacitance increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the etch stop layer from high to low values, selecting materials with lower capacitance while maintaining sufficient etch selectivity and manufacturing precision through optimized layer thickness and composition
3Object-generated harmful factors
If dielectric layers are placed in direct contact, then capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent removes intermediate dielectric layers between contact structures, placing dielectric layers in direct contact to reduce capacitance, while managing the resulting manufacturing complexity through simplified process steps and optimized deposition parameters
4Productivity
If feature sizes are reduced to increase integration density, then productivity is improved, but reliability deteriorates due to misalignment and high resistance
Solution Approach 1:
The patent optimizes multiple parameters including plasma treatment conditions, etch stop layer thickness, and deposition parameters to maintain alignment accuracy and reduce resistance in scaled-down features, enabling continued productivity improvement without sacrificing reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of self-aligned interconnection structures, reduces resistance, and lowers capacitance by eliminating SAM-related issues and the need for high dielectric constant etch stop layers, while maintaining mechanical strength and alignment accuracy.
Implementation Method 1
H2 plasma pre-treatment
Data Source
AI summary
An interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, a conductive layer, a liner layer, a third dielectric layer, a second conductive feature, and a first capping layer. The first conductive feature is disposed in the first dielectric layer. The second dielectric layer is formed on the first dielectric layer, and the second dielectric layer is in direct contact with the first dielectric layer. The conductive layer is disposed in the second dielectric layer. The liner layer is disposed between the conductive layer and the second dielectric layer. The third dielectric layer is formed on the second dielectric layer. The second conductive feature is disposed in the third dielectric layer. The first capping layer is disposed between the second conductive feature and the third dielectric layer.