Self-Aligned Interconnection Structure for FinFETs
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Solution Overview
Problem
Advanced integrated circuits face challenges in interconnection reliability due to narrow fin active regions and shrinking device sizes, leading to issues like contact bridging and misalignment in FinFETs, which affect circuit performance and reliability.
Innovation Solution
A self-aligned interconnection structure and method are developed, using a multi-layer mandrel and dielectric material approach with patterning and etching processes to form conductive features that are self-aligned with underlying metal features, minimizing bridging issues and ensuring accurate alignment through the use of gating posts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device sizes are shrunk for high-density gate pitch requirement, then productivity is improved, but manufacturing precision deteriorates due to interconnection misalignment and bridging issues
Solution Approach 1:
The patent applies preliminary action by forming mandrels and dielectric layers before the final interconnection patterning step. The mandrels are positioned and secured with dielectric material in advance, creating a self-aligned structure that guides subsequent etching processes. This preliminary structuring ensures that even as device densities increase, the alignment between metal lines and vias remains precise because the physical mandrel structure dictates the positioning rather than relying solely on lithographic alignment at scaled dimensions.
2Productivity
If contact size is shrunk to maintain contact resistance, then productivity is improved, but reliability deteriorates due to material integration and processing constraints
Solution Approach 1:
The patent introduces mandrels as intermediary structures that facilitate the formation of reliable contacts at reduced sizes. These mandrels serve as temporary physical guides and support structures during the patterning and etching processes. By providing this intermediary framework, the process can achieve precise placement of smaller contacts without compromising their structural integrity or electrical performance, as the mandrels ensure proper alignment and spacing throughout the fabrication sequence.
3Power
If fin width is narrowed for short channel control, then device performance is improved, but reliability worsens due to contact to S/D landing margin degradation
Solution Approach 1:
The patent applies preliminary action by pre-forming mandrels that extend into the S/D regions before contact patterning. These mandrels are positioned to account for the narrow fin dimensions, providing a physical reference structure that ensures adequate landing margins are maintained. The mandrels are formed in advance with precise spacing that compensates for the reduced S/D region size, allowing contacts to be reliably formed despite the narrower fins required for short channel control.
4Manufacturing precision
If self-aligned interconnection structure is implemented, then manufacturing precision is improved, but device complexity increases due to multi-layer mandrel and dielectric approach
Solution Approach 1:
The patent applies segmentation by dividing the interconnection formation process into distinct modular stages: mandrel formation, dielectric layer deposition, etching, and mandrel removal. Each stage handles a specific function independently, with the mandrel structure serving as a reusable template across multiple interconnection layers. This segmented approach manages complexity by breaking down the self-alignment challenge into discrete, controllable steps rather than attempting to achieve alignment in a single complex operation.
Solution Approach 2:
The mandrel structure serves multiple functions throughout the fabrication process: it acts as a positioning template, a physical barrier during etching, and a guide for subsequent layer formation. By making the mandrel multi-functional, the patent reduces the need for separate alignment structures for each function, thereby managing overall device complexity while maintaining high manufacturing precision across multiple interconnection layers.
Data Source
AI summary
The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.