Self-Aligned Interconnection Structure With Selective Barrier Layers
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Solution Overview
Problem
The semiconductor industry faces challenges with reliability, high capacitance, and high resistance in integrated circuits due to the increasing density of components and reduced feature sizes, which existing self-aligned contact processes struggle to address effectively.
Innovation Solution
A self-aligned interconnection structure is developed, featuring a dielectric layer, a conductive feature, a capping layer, and selectively formed barrier layers, where the barrier layers are formed only on the conductive feature to reduce capacitance and resistance, and a pre-treatment process is used to enhance selectivity, avoiding the use of self-assembled monolayers that can cause residue and unwanted reactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned contact process is used to avoid misalignment, then manufacturing precision is improved, but capacitance and resistance increase
Solution Approach 1:
The patent applies local quality by forming barrier layers selectively only on the conductive feature surfaces that require protection, rather than uniformly across all surfaces. The barrier layers are deposited only where needed (on sidewalls and top surfaces of conductive features) while leaving other areas untreated, thereby reducing overall capacitance and resistance without compromising alignment precision.
Solution Approach 2:
The patent segments the barrier layer formation process into multiple selective deposition steps, where barrier layers are formed on different surfaces (sidewalls, top surfaces) at different stages. This segmentation allows precise control over where barrier layers are present, optimizing the balance between alignment precision and electrical performance.
2Manufacturing precision
If self-assembled monolayers are used to enhance selectivity, then manufacturing precision is improved, but residue and unwanted reactions occur
Solution Approach 1:
The patent extracts and eliminates the self-assembled monolayer step from the fabrication process. Instead of using SAMs to achieve selectivity, the patent employs alternative selective deposition methods that do not leave residue or cause unwanted reactions, thereby maintaining manufacturing precision while removing harmful factors.
Solution Approach 2:
The patent replaces the self-assembled monolayer (a complex, residue-prone material) with simpler, cleaner deposition methods that achieve the same selectivity function without the harmful side effects. The alternative methods use materials and processes that do not leave persistent residue on the conductive features.
Data Source
AI summary
A self-aligned interconnection structure includes a dielectric layer, a conductive feature, a capping layer, a first barrier layer and a second barrier layer. The conductive feature is formed in the dielectric layer, and the conductive feature has a top surface. The capping layer is disposed on the top surface of the conductive feature, and the capping layer does not cover the dielectric layer. The first barrier layer is disposed on the capping layer, and the first barrier layer does not cover the dielectric layer. The second barrier layer covers the first barrier layer and the dielectric layer, and the first barrier layer and the second barrier layer are formed of different materials.