Self-Aligned Interconnects for Semiconductor Devices
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Solution Overview
Problem
The semiconductor industry faces challenges in forming and aligning conductive layers in multilayer devices as they scale down, leading to via alignment issues due to critical dimension uniformity variations and lithography overlay errors, which complicates the fabrication of interconnect structures.
Innovation Solution
A via-free interconnect structure is developed where metal lines are self-aligned, eliminating the need for vias by forming a self-aligned interconnect between conductive layers through a method involving etching and chemical mechanical planarization (CMP) processes, allowing direct electrical contact between metal layers without the requirement for precise via alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via alignment methods are used to connect conductive layers, then electrical connections between layers can be established, but manufacturing precision deteriorates due to critical dimension uniformity variations and lithography overlay errors
Solution Approach 1:
The patent removes the via structure entirely from the interconnect architecture. Instead of using vias to connect metal lines between layers, the invention allows metal lines to extend directly across ILD boundaries and contact underlying metal lines, eliminating the alignment-critical via component and its associated manufacturing precision problems
Solution Approach 2:
Conventional design places vias at intersections to connect layers, requiring precise alignment. This patent inverts the approach by allowing metal lines to cross ILD boundaries without vias, making the ILD layers conform to the metal line geometry rather than requiring metal lines to align with predefined via locations
2Reliability
If via alignment steps are implemented to ensure precise connection, then electrical contact reliability improves, but device complexity increases due to additional alignment and manufacturing steps
Solution Approach 1:
The patent eliminates the via formation and alignment steps from the fabrication process. By removing the via structure and its associated alignment requirements, the invention reduces fabrication complexity while maintaining interconnect reliability through direct metal-to-metal contact across ILD boundaries
Solution Approach 2:
The patent merges the metal line formation process with the interlayer connection process. Instead of separate via formation and metal line deposition steps, the metal lines are deposited to naturally extend across ILD boundaries and contact underlying lines, combining multiple functions into a single integrated process
3Reliability
If traditional interconnect structures with vias are used, then electrical connections can be made between conductive layers, but manufacturing costs increase due to complex alignment requirements and additional process steps
Solution Approach 1:
By removing the via structure and its associated alignment and fabrication steps, the patent reduces manufacturing complexity and cost while maintaining electrical connection functionality through direct metal line contact across ILD layers
Solution Approach 2:
The metal lines self-align and self-connect across ILD boundaries through the natural geometry of the interconnect layout. The structure automatically ensures electrical contact without requiring external alignment processes or additional manufacturing steps
Data Source
AI summary
A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.