Self-Aligned Isolation Structure for DRAM Contact Alignment
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Solution Overview
Problem
The reduction of device size in dynamic random access memory (DRAM) leads to alignment issues during lithography processes, resulting in a decrease in the contact area between the active area and the capacitor contact, causing increased resistance and read/write time failures.
Innovation Solution
A method of fabricating a memory device with a self-aligned isolation structure is developed, which involves forming a substrate with distinct regions, creating word line sets, and using etching processes to form a trench and dielectric layers to improve alignment and reduce process steps, thereby enhancing the contact area and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-lithography processes are used to form the isolation structure and capacitor contact separately, then the isolation structure can be formed deeper than buried word lines, but alignment issues occur resulting in reduced contact area between active area and capacitor contact
Solution Approach 1:
The isolation structure serves as its own alignment reference for forming the capacitor contact. The capacitor contact is formed self-aligned with the isolation structure, eliminating the need for separate lithography alignment and ensuring the contact area is not reduced by misalignment.
Solution Approach 2:
The isolation structure is formed first, and then the capacitor contact is formed using the isolation structure as a template or mask. This preliminary formation of the isolation structure establishes the alignment reference before the capacitor contact is created, preventing alignment issues.
2Manufacturing precision
If multi-lithography processes are used to form the isolation structure and capacitor contact respectively, then the isolation structure can be formed deeper than buried word lines, but the number of process steps increases resulting in higher process cost
Solution Approach 1:
The formation of the isolation structure and capacitor contact is merged into a single lithography process. The same lithography step that defines the isolation structure also defines the capacitor contact position, reducing the total number of lithography processes while maintaining precise depth control of the isolation structure.
Solution Approach 2:
The lithography process is made multi-functional by using it to define both the isolation structure and the capacitor contact in a single step. This universal approach eliminates the need for separate dedicated lithography steps for each feature.
3Volume of moving object
If the contact area between active area and capacitor contact is reduced due to misalignment, then device size can be reduced, but resistance between active area and capacitor contact increases causing read/write time failure
Solution Approach 1:
The capacitor contact formation uses the isolation structure as a self-aligned reference, ensuring that the contact area is maximized regardless of device size reduction. This self-alignment mechanism prevents misalignment-induced contact area reduction that would increase resistance and cause read/write failures.
Data Source
AI summary
A method of fabricating a memory device includes providing a substrate having a first region and a second region. A first dielectric layer is formed on the substrate in the first region. A conductive layer is formed on the substrate in the second region. A top surface of the conductive layer is lower than a top surface of the first dielectric layer. A second dielectric layer is formed on the substrate. A portion of the second dielectric layer and a portion of the conductive layer are removed to form a first opening in the conductive layer and the second dielectric layer in the second region. The first opening exposes a surface of the substrate. A portion of the substrate in the second region is removed to form a trench in the substrate in the second region. A third dielectric layer is formed in the trench and the first opening.


