Self-Aligned Isolation Insulating Layers in Semiconductor Fin Regions
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Solution Overview
Problem
Conventional methods struggle to form precise isolation insulating layers in fin regions of semiconductor devices, leading to misalignment issues and increased leakage current, particularly as device sizes decrease below 20 nm.
Innovation Solution
The development of semiconductor devices with self-aligned isolation insulating layers formed between fin regions, using techniques such as oxidizing fin regions to create discrete isolation islands, which separate fin subregions and prevent short circuits between gate electrodes and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning methods are used to form isolation insulating layers in fin regions, then the manufacturing process is simple, but misalignment occurs between photolithography processes and fin regions leading to leakage current
Solution Approach 1:
The method performs preliminary actions by forming mandrels and isolation insulating layers before final gate patterning. The mandrels are positioned to define where isolation layers will be deposited, ensuring proper alignment is established early in the process before subsequent lithography steps occur.
Solution Approach 2:
Mandrels serve as intermediary structures that facilitate the formation of isolation insulating layers with proper alignment. These temporary structures guide the deposition process and are later removed, having served their purpose of ensuring precise positioning of the isolation layers relative to fin regions.
2Productivity
If device sizes are reduced to increase integration density, then more devices fit in the same area, but conventional patterning methods become increasingly difficult to implement
Solution Approach 1:
The process segments the patterning task into multiple steps: first forming mandrels, then depositing isolation layers, removing mandrels, and finally forming gates. This segmentation allows each step to be performed with relaxed alignment requirements compared to attempting to pattern all features in a single lithography step at the reduced scale.
Solution Approach 2:
The method introduces a temporal dimension to the patterning process by using sequential deposition and removal steps rather than relying solely on planar lithography alignment. The mandrel-isolation-mandrel removal sequence creates alignment in the time dimension, effectively bypassing the limitations of lateral alignment at reduced feature sizes.
3Reliability
If isolation insulating layers are formed to separate fin regions, then leakage current between gates and source/drain regions is prevented, but misalignment between photolithography processes and fin regions occurs
Solution Approach 1:
The method performs preliminary actions by forming mandrels and isolation insulating layers before final gate patterning. The mandrels are positioned to define where isolation layers will be deposited, ensuring proper alignment is established early in the process before subsequent lithography steps occur.
Solution Approach 2:
Mandrels serve as intermediary structures that facilitate the formation of isolation insulating layers with proper alignment. These temporary structures guide the deposition process and are later removed, having served their purpose of ensuring precise positioning of the isolation layers relative to fin regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor devices by preventing leakage current and improving pattern precision, allowing for more efficient integration density and reduced misalignment in smaller device sizes.
Implementation Method 1
forming a discrete isolation insulating island comprising an oxide layer in the fin region by oxidizing a portion of the fin region
Data Source
AI summary
The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.