Self-aligned junction structures for semiconductor finFETs
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Solution Overview
Problem
The formation of nFET and pFET devices on a wafer requires complex semiconductor fabrication processes due to the need for two masking and lithography steps, leading to misalignment issues and the creation of bumps between devices, which complicates downstream processes and increases time and cost.
Innovation Solution
The use of epitaxial grown fin structures with sidewall liners allows for self-aligned junction integration, enabling nFET and pFET patterning with a single mask and eliminating the formation of bumps between devices, by depositing amorphous Si material, forming sidewall barrier layers, and replacing fin structures with epitaxial grown ones, thereby simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two separate masking and lithography steps are used for nFET and pFET patterning, then device formation is achieved, but manufacturing time and cost increase significantly
Solution Approach 1:
The patent merges the patterning of nFET and pFET devices into a single masking and lithography step by using a shared mandrel structure. The mandrel is used to define both nFET and pFET regions simultaneously, eliminating the need for two separate masking steps and reducing alignment complexity while maintaining manufacturing precision.
Solution Approach 2:
The patent performs preliminary actions by forming the mandrel structure and sidewall spacers before the final device patterning. The mandrel is created first, followed by sidewall spacer formation, which then serves as the basis for defining both nFET and pFET regions in a single lithography step, streamlining the overall manufacturing process.
2Manufacturing precision
If two separate masking steps are used for nFET and pFET, then device patterning is complete, but mask misalignment creates gaps and bumps between devices
Solution Approach 1:
The patent combines the patterning of nFET and pFET into a single lithography step using a common mandrel, eliminating mask misalignment issues entirely. The shared mandrel ensures perfect alignment between nFET and pFET regions, preventing gaps and bumps that would otherwise require additional correction steps.
Solution Approach 2:
The mandrel acts as an intermediary structure that mediates the patterning process for both nFET and pFET devices. By using the mandrel as a common reference, the patent eliminates direct mask-to-mask alignment requirements, thereby preventing misalignment-induced defects without adding fabrication complexity.
3Productivity
If bumps are formed between nFET and pFET due to mask misalignment, then device fabrication continues, but downstream processes become complicated and time-consuming
Solution Approach 1:
The patent applies preliminary anti-action by preventing bump formation in the first place through single-step patterning. By using a shared mandrel and sidewall spacers to define both nFET and pFET regions simultaneously, the process eliminates the root cause of bumps (mask misalignment), thereby avoiding downstream complications and maintaining high manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces manufacturing time and cost by eliminating the need for additional masking steps and preventing bumps between nFET and pFET devices, simplifying the fabrication process and improving alignment accuracy.
Implementation Method 1
a plurality of epitaxial grown fin structures for first type devices; and a plurality epitaxial grown fin structures for second type devices
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to self-aligned junction structures and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for first type devices; and a plurality epitaxial grown fin structures for second type devices having sidewall liners.