Self-Aligned LDD Thin-Film Transistor Fabrication via Masking Layer Thickness
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Solution Overview
Problem
Conventional methods for fabricating thin-film transistors (TFTs) with self-aligned lightly doped drain (LDD) structures require separate masking and doping steps, leading to misalignment issues and affected electrical properties due to the need for a separate masking step and doping procedure.
Innovation Solution
A process where a masking layer with varying thickness is used to simultaneously form heavily doped and lightly doped regions in a semiconductor layer during a single doping operation, allowing for self-aligned LDD formation without additional masking steps, and a multi-gate structure with LDD regions formed laterally adjacent to gate layers, using shielding regions to control doping concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a separate masking step and doping procedure are used to form LDD regions, then the doping process can be controlled, but misalignment occurs and electrical properties are affected
Solution Approach 1:
The patent combines the masking and doping steps into a single simultaneous operation. The gate insulating layer serves as the mask while dopant is introduced, eliminating the need for a separate masking step and achieving self-alignment that prevents misalignment errors.
Solution Approach 2:
The gate insulating layer automatically serves as the masking layer for the doping process. By controlling its thickness, the system self-regulates the doping depth and LDD region formation without requiring external masking materials or additional alignment steps.
2Reliability
If a masking layer with varying thickness is used for single doping operation, then self-aligned LDD formation is achieved, but the process requires precise thickness control
Solution Approach 1:
The patent utilizes thickness as a controllable parameter of the gate insulating layer to regulate doping concentration and LDD region formation. By adjusting the thickness parameter, the system achieves different doping levels and electrical characteristics in a single doping operation.
3Object-generated harmful factors
If conventional separate doping steps are used, then doping concentration can be adjusted, but leakage current increases due to misalignment
Solution Approach 1:
The gate insulating layer acts as an intermediary that precisely controls dopant distribution. It mediates between the dopant source and the semiconductor substrate, ensuring that LDD regions are formed with correct alignment and concentration gradients, thereby reducing leakage current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage current, eliminates misalignment errors, and simplifies the doping process by forming symmetrical LDD regions and source/drain regions simultaneously, enhancing the accuracy and electrical performance of TFTs.
Implementation Method 1
The masking layer is permeable to dopant, but provides a barrier to the dopant such that the covered region is lightly doped compared to the heavily doped region
Implementation Method 2
The thickness of the mask is chosen in relation to the doping parameters (e.g., time, dopant, concentration, etc.) to result in the desired doping levels
Data Source
AI summary
A self-aligned LDD TFT and a fabrication method thereof. The method includes providing a semiconductor layer. A first masking layer is provided over a first region of the semiconductor layer, said first masking layer comprising a material that provide a permeable barrier to a dopant. The semiconductor layer is exposed, including the first region covered by the first masking layer, to the dopant, wherein the first region covered by the first masking layer is lightly doped with the dopant in comparison to a second region not covered by the first masking layer.