Self-Aligned LDMOS Gate Oxide Engineering
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Solution Overview
Problem
Conventional LDMOS devices face a tradeoff between breakdown voltage (BVdss), on-state resistance (Rdson), and safe operating area (SOA), where increasing BVdss results in higher Rdson, and BVdss and SOA have conflicting relationships, making it challenging to achieve a combination of higher BVdss, lower Rdson, and higher SOA.
Innovation Solution
A self-aligned LDMOS device design featuring a gate with a gate oxide and oxide spacer on the source side, a source region with a tap and source spacer embedded in a source well, and a drain region in a high voltage well, where the source spacer is fully under the oxide spacer, allowing for optimized spacing and reduced on-state resistance while maintaining high breakdown voltage and safe operating area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the drift region is increased to raise breakdown voltage, then breakdown voltage is improved, but on-state resistance increases
Solution Approach 1:
The patent applies local quality by creating different doping concentrations in specific regions: a first doping concentration in the drift region and a second doping concentration in the extension region, where the second concentration is higher than the first. This localized variation in doping quality allows the drift region to maintain high breakdown voltage while the extension region provides lower resistance paths, thus resolving the contradiction between high breakdown voltage and low on-state resistance.
2Strength
If the pitch between drain and source is increased to raise breakdown voltage, then breakdown voltage is improved, but device area increases
Solution Approach 1:
The patent extends the drift region laterally beyond the gate edges into extension regions, utilizing the lateral dimension to increase the effective drift region area without increasing the vertical pitch between drain and source. This dimensional approach allows maintaining high breakdown voltage while keeping the device footprint compact, resolving the contradiction between breakdown voltage and device area.
3Strength
If the drift region is optimized for high breakdown voltage, then breakdown voltage is improved, but safe operating area may be compromised
Solution Approach 1:
The patent segments the drift region into two distinct parts: a main drift region under the gate with a first doping concentration optimized for breakdown voltage, and extension regions beyond the gate edges with a second higher doping concentration that provides low-resistance current paths. This segmentation allows the device to achieve both high breakdown voltage and large safe operating area by distributing different functional requirements to different segments.
Data Source
AI summary
The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.