Self-Aligned Liner Protects PL Gate During Silicide Formation
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Solution Overview
Problem
The miniaturization of semiconductor memory cells leads to damage during fabrication, resulting in deformed or non-uniform gate profiles, which can cause electrical issues such as resistance, reliability, retention, and disturb problems due to the silicide being formed too closely to the insulation layer.
Innovation Solution
A method involving the use of a semiconductor structure with specific liner layers, including a silicon nitride layer with an overhang profile and a low temperature oxide layer, to protect the polysilicon gates during etching, ensuring a self-aligned source formation and maintaining a sufficient distance between the silicide and the insulating layer, thereby preventing damage and achieving a uniform silicide profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate is miniaturized to scale down memory cells, then productivity and integration density are improved, but manufacturing precision deteriorates due to gate damage during fabrication
Solution Approach 1:
The patent applies preliminary action by forming the liner layer on the gate structure before the etching process. This liner layer serves as a protective barrier that prevents etchant damage to the gate during fabrication. The liner is deposited in advance and then selectively removed after the etching is complete, ensuring the gate remains undamaged throughout the miniaturization process while maintaining manufacturing precision
Solution Approach 2:
The patent implements beforehand cushioning by introducing a liner layer that acts as a cushioning barrier between the etchant and the gate structure. This liner layer absorbs or mitigates the harmful effects of the etching process on the gate, preventing damage while allowing the etching to proceed. The liner is subsequently removed to leave a clean, undamaged gate surface
2Area of stationary object
If the silicide is formed too closely to the insulating layer, then area is reduced, but reliability deteriorates due to electrical issues
Solution Approach 1:
The patent uses preliminary action by forming the liner layer before silicide formation. The liner layer maintains a controlled spacing between the gate and the insulating layer during the silicide formation process, ensuring that the silicide does not form too closely to the insulating layer. This preliminary protective structure ensures reliable electrical performance while allowing minimal spacing
3Device complexity
If the gate profile is deformed or non-uniform, then manufacturing complexity is reduced, but reliability deteriorates due to electrical issues
Solution Approach 1:
The patent applies preliminary action by depositing the liner layer on the gate structure before etching and silicide formation. This liner layer maintains a uniform gate profile throughout the fabrication process by protecting against etchant damage and providing a consistent surface for subsequent processing. The liner is removed after processing to leave a clean, uniform gate surface that ensures reliable electrical performance
Solution Approach 2:
The patent introduces the liner layer as an intermediary between the gate structure and the etchant/silicide formation processes. This intermediary layer protects the gate from direct exposure to harmful processes while maintaining profile uniformity. The liner acts as a mediator that enables safe processing without compromising gate integrity or electrical performance
Data Source
AI summary
A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.