Self-Aligned Conductive Lines With Barrier Layer Isolation

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Solution Overview

Problem

The semiconductor industry faces challenges in aligning conductive lines during double patterning/double etch processes, leading to misalignment and potential short circuits as feature density increases, making it difficult to achieve high areal and volume density of digital circuits.

Innovation Solution

The implementation of a barrier layer between conductive lines, which acts as an insulating barrier to prevent electrical connections and allows for self-aligned formation of additional conductive lines, reducing the risk of misalignment and short circuits by maintaining a precise spacing between lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If double patterning/double etch process is used to increase feature density, then areal and volume density of digital circuits is improved, but alignment precision between structures made in first and second patterning/etch processes deteriorates

Engineering Contradiction:
Improvefeature densityVSAvoidalignment precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

A barrier layer is formed over the first conductive lines before the second patterning/etch process. This preliminary action creates a protective structure that defines the spacing for subsequent conductive lines, ensuring precise alignment is maintained even as feature density increases through double patterning

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The barrier layer acts as an intermediary structure between the first and second sets of conductive lines. It provides a physical reference that mediates the alignment process, allowing the second conductive lines to be self-aligned to the first set while maintaining precise spacing and preventing misalignment

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If conductive lines are placed closer together to increase areal density, then productivity is improved, but the risk of short circuits due to misalignment increases

Engineering Contradiction:
Improveareal densityVSAvoidrisk of short circuits
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The barrier layer is formed in advance over the first conductive lines, establishing a protective framework before the second patterning process. This preliminary structure ensures that even when conductive lines are placed closer together to increase areal density, the spacing is precisely controlled and short circuits are prevented

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The barrier layer provides a protective cushion between conductive lines, preventing direct contact and potential short circuits. This beforehand protection is built into the structure before misalignment could occur, allowing closer spacing while maintaining reliability

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS20240379418A1Self-aligned lines and methods for fabricating the same
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379418A1 patent drawing
  • US20240379418A1 patent drawing
  • US20240379418A1 patent drawing

AI summary

A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.