Self-Aligned Low Noise JFET Using Gate Electrode and Spacers

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Solution Overview

Problem

High-performance precision analog applications require transistors with extremely low noise and high disturbance immunity, which existing JFETs do not fully meet due to noise introduction from additional materials used for isolation in semiconductor substrates.

Innovation Solution

The method involves self-aligning active regions of the JFET with patterned gate electrode material and sidewall spacers, eliminating the need for additional isolating materials and allowing a uniform gate dielectric layer for uninhibited current flow, thereby reducing noise and enhancing immunity to disturbances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional materials are used to isolate active regions in semiconductor substrate, then active regions are electrically isolated from one another, but noise is introduced into the JFET

Engineering Contradiction:
Improvedisturbance immunityVSAvoidnoise
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent removes additional isolating materials from the semiconductor substrate by utilizing the gate electrode material and sidewall spacers to define active region boundaries. This extraction eliminates the noise-generating materials while preserving electrical isolation through the self-aligned structure, directly resolving the contradiction between disturbance immunity and noise generation

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The gate electrode material and sidewall spacers serve multiple functions: they define the boundaries of active regions for electrical isolation while simultaneously providing the gating function. This multi-functionality eliminates the need for separate isolating materials, achieving both disturbance immunity and low noise through a unified structure

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Object-generated harmful factors

If additional isolating materials are removed to reduce noise, then noise is reduced in the JFET, but active regions may lack proper electrical isolation

Engineering Contradiction:
ImprovenoiseVSAvoiddisturbance immunity
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The gate electrode material and sidewall spacers are self-aligned to automatically define the boundaries of active regions. This self-service mechanism provides both electrical isolation and noise reduction without requiring additional isolating materials, as the structure defines itself through the alignment of existing components

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The sidewall spacers act as intermediaries between the gate electrode material and the active regions, providing the necessary electrical isolation. These spacers mediate the boundary definition and isolation function, enabling noise reduction while maintaining disturbance immunity through the intermediary structure

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If gate dielectric layer is removed to allow direct contact, then current flow is enhanced, but interface uniformity and current control are compromised

Engineering Contradiction:
Improvecurrent flowVSAvoidinterface uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent maintains the gate dielectric layer but optimizes its thickness and properties to achieve the desired balance. By changing the dielectric parameters (thickness, material properties), the structure enables sufficient current flow while preserving interface uniformity and control, resolving the contradiction between productivity and manufacturing precision

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7745274B2Gate self aligned low noise JFET
Publication Date: 2010.06.29 TEXAS INSTRUMENTS INC
  • US7745274B2 patent drawing
  • US7745274B2 patent drawing
  • US7745274B2 patent drawing

AI summary

The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.