Self-Aligned High Voltage LDMOS on SOI Substrates
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Solution Overview
Problem
Conventional lateral drain-diffused (LD) transistors formed on bulk substrates are not compatible with crystalline-on-insulator (COI) substrates, such as silicon-on-insulator (SOI) substrates, leading to disconnected drift regions and inoperability, and there is a need for high voltage transistors with improved RF/Analog performance compatible with CMOS applications.
Innovation Solution
The method involves forming a crystalline-on-insulator substrate with a buried insulator layer, creating drift and device isolation trenches, and filling them with isolation material to form a transistor with specific diffusion regions and drift wells, allowing for the integration of LD transistors that are compatible with SOI substrates and provide improved high voltage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional LD transistors are formed on bulk substrates, then the drift regions are disconnected from the channel, but the transistors are inoperable on COI substrates
Solution Approach 1:
The patent introduces a new dimensional approach by forming drift isolation trenches that extend vertically through the buried oxide layer to connect the drift region with the channel in the surface substrate. This vertical connection through the insulator layer resolves the disconnection problem inherent in conventional planar LD transistors on COI substrates, enabling current flow while maintaining substrate isolation benefits.
Solution Approach 2:
The patent uses drift isolation trenches filled with conductive material as an intermediary structure to bridge the drift region and channel across the buried oxide layer. This intermediary conductive path allows electrical connection through the insulator, solving the fundamental incompatibility between conventional LD transistor structures and COI substrates.
2Loss of energy
If SOI substrates are used, then power consumption is reduced and latchup resistance is improved, but conventional LD transistors become incompatible
Solution Approach 1:
The patent extends the drift region connectivity into the vertical dimension by etching through the buried oxide layer, allowing conventional LD transistor operation on SOI substrates while preserving the low power consumption and latchup resistance benefits provided by the isolated surface substrate.
Solution Approach 2:
The patent modifies the structural parameters of the LD transistor by introducing deep drift isolation trenches that penetrate the buried oxide layer, changing the electrical connectivity parameters while maintaining the physical isolation benefits of the SOI substrate for low power operation.
3Reliability
If drift isolation trenches are formed to connect drift regions, then transistor operability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs drift isolation trench formation early in the fabrication process, before transistor assembly, using the same mask alignment references. This preliminary action simplifies subsequent processing steps and reduces overall manufacturing complexity despite the additional trench formation requirement.
Solution Approach 2:
The drift isolation trenches serve multiple functions: they provide electrical connection between drift regions and channels, act as isolation structures, and define alignment references for subsequent processing steps. This multi-functionality reduces the need for separate dedicated structures, simplifying the overall manufacturing process.
Data Source
AI summary
Devices and methods for forming a device are disclosed. The method includes providing a crystalline-on-insulator substrate having a bulk substrate and a surface substrate separated by a buried insulator layer. The surface substrate is defined with a device region. A transistor having a gate is formed in the device region. A first diffusion region is formed adjacent to a first side of the gate and a second diffusion region is formed adjacent to and displaced away from a second side of the gate. At least a first drift isolation region is formed in the surface substrate adjacent to and underlaps the second side of the gate. A drift well is formed in the surface substrate encompassing the first drift isolation region. A device isolation region surrounding the device region is formed in the surface substrate. The device isolation region includes a second depth which is deeper than a first depth of the first drift isolation region.