Self-Aligned Interconnection Structure for Direct M2 Routing

The patent transitions from a planar interconnection architecture to a three-dimensional stacked architecture. Multiple interconnection layers (M1, M2, M3, M4) are vertically stacked above the semiconductor device, with via structures (Via1, Via2, Via3) providing vertical connections between layers. This vertical stacking enables efficient signal transmission between different interconnection layers while maintaining a compact die footprint, as the expanded connectivity is achieved in the vertical dimension rather than requiring lateral expansion of the die area.

The patent merges the formation of via structures and contact structures into a unified self-aligned process. The lower conductor portion of each via structure serves as the contact structure, eliminating the need for separate contact and via formation steps. This integrated approach ensures automatic alignment between what would traditionally be separate Via1 and contact structures, as they are formed as a single continuous conductive element through the dielectric layer, thereby achieving precise alignment without requiring additional alignment steps or complex manufacturing processes.

The patent segments the interconnection path into distinct functional portions. The via structure is divided into an upper conductor portion that connects to the M2 interconnection layer and a lower conductor portion that serves as the contact structure connecting to the gate or diffusion region. This segmentation allows the lower conductor portion to provide direct vertical connection from the gate/diffusion region through the dielectric layer to M2, bypassing the need for lateral routing through the M1 interconnection layer, thereby enabling more efficient signal transmission paths.