Self-Aligned Memory Cell Fabrication via Mask Trimming
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Solution Overview
Problem
Conventional semiconductor fabrication processes face limitations in forming features smaller than the minimum feature size, particularly below 100 nm, due to the wavelength of light used in lithography, leading to challenges in manufacturing small dimension memory devices with tight process variation specifications.
Innovation Solution
A self-aligned manufacturing method for memory devices involves forming an electrode layer with a patch of memory material using mask trimming, where a resist layer is reduced to sub-lithographic dimensions through dry etching, allowing for the formation of narrow structures compatible with peripheral circuits on integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography with visible light is used, then the manufacturing process is simple and well-established, but the minimum feature size cannot be reduced below approximately 100 nm due to the wavelength of light
Solution Approach 1:
The patent divides the lithography process into two distinct stages: first, forming a preliminary pattern at a larger size using conventional lithography; second, creating the final sub-lithographic pattern through self-aligned etching and spacer formation. This segmentation allows each stage to operate within its optimal capability range, avoiding the need for single-step ultra-precise lithography.
Solution Approach 2:
The patent performs preliminary patterning at a relaxed dimensional constraint using conventional lithography, then uses this preliminary structure as a template for subsequent self-aligned processing. The preliminary pattern serves as a foundation that guides the formation of the final narrow features, ensuring precision without requiring the lithography step to directly achieve the final dimensions.
2Manufacturing precision
If multiple lithography cycles are used to achieve sub-lithographic features, then the manufacturing precision can be improved, but the production time and resource costs increase significantly
Solution Approach 1:
The patent merges multiple patterning operations into a single lithography exposure step by utilizing self-aligned etching and spacer formation. The preliminary pattern and final pattern are created in one lithography cycle, with subsequent steps automatically aligning to the preliminary structure, thereby combining what would traditionally require multiple separate lithography cycles into one integrated process flow.
Solution Approach 2:
The patent employs self-aligned etching where the etch process automatically follows the preliminary pattern without requiring additional alignment steps. The spacers form self-aligned to the etched features, and the entire sequence proceeds without manual intervention for alignment, allowing the process to serve itself and achieve high precision without multiple lithography cycles.
3Manufacturing precision
If shorter-wavelength sources such as x-rays are used, then the minimum feature size can be reduced, but the manufacturing complexity and equipment requirements increase dramatically
Solution Approach 1:
The patent changes the critical parameter from lithography wavelength to etch selectivity and spacer thickness control. Instead of using shorter-wavelength light, the process achieves sub-lithographic dimensions by precisely controlling the etching depth and spacer dimensions, which can be done with conventional lithography wavelengths combined with advanced etch and deposition processes.
Solution Approach 2:
The patent introduces spacers as an intermediary structure that translates the preliminary pattern into the final narrow features. The spacers act as a mediator between the lithography step and the final pattern, allowing the lithography to operate at relaxed dimensions while the spacer formation process achieves the required sub-lithographic precision through controlled deposition and etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of memory cells with small dimensions and low reset currents, meeting tight process variation specifications, and reduces the need for multiple lithography cycles, thereby decreasing time and resource costs while achieving sub-lithographic feature sizes.
Implementation Method 1
a resist layer is reduced to sub-lithographic dimensions through dry etching
Data Source
AI summary
A method for manufacturing a self aligned narrow structure over a wider structure based on mask trimming. A method for manufacturing a memory device comprises forming an electrode layer on a substrate which comprises circuitry made using front-end-of-line procedures. The electrode layer includes a first electrode and a second electrode, and an insulating member between the first and second electrodes for each phase change memory cell to be formed. A patch of memory material is formed on the top surface of the electrode layer across the insulating member for each memory cell to be formed. The patch and the first and second electrodes are formed using a self-aligned process based on mask trimming.