Self-Aligned Metal Gate for Vertical FETs
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Solution Overview
Problem
Conventional CMOS processing for FinFETs faces challenges with work function metal recess and encapsulation affecting device reliability, particularly in VFETs, leading to higher voltage thresholds and performance issues due to interface characteristic alterations after high-temperature processing.
Innovation Solution
A method involving forming a fin structure over a substrate, etching a dummy gate to expose a top portion, depositing dielectric layers, and stripping the dummy gate to create a recess for a high-k metal gate (HKMG) deposition, which directly contacts the fin structure, allowing for improved control and reduced defects in manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If work function metal is recessed and encapsulated in conventional VFET processing, then device fabrication can proceed, but interface characteristics are altered after high-temperature processing leading to higher voltage thresholds and performance degradation
Solution Approach 1:
The patent removes the work function metal from the top region of the VFET structure through selective etching, extracting the problematic element that causes interface characteristic alterations. This extraction eliminates the source of voltage threshold shifts and performance degradation while maintaining the metal's presence in regions where it provides beneficial work function control.
Solution Approach 2:
The patent applies different structural configurations to different regions of the device. The work function metal is retained in the bottom region where it provides appropriate work function control, while the top region is modified to expose the fin structure and eliminate the problematic metal-dielectric interface. This local differentiation resolves the contradiction by optimizing each region for its specific function.
2Ease of operation
If work function metal is used for gate fabrication in VFETs, then gate control is achieved, but the top portion of the metal is exposed to RIE, air, wet etching, and encapsulation causing Vt variation and dielectric leakage
Solution Approach 1:
The patent selectively removes the work function metal from the top region where it is exposed to harmful processing steps. By extracting the metal from this vulnerable location, the patent eliminates the harmful interactions between the metal interface and the fin structure that cause Vt variation and dielectric leakage, while preserving gate control functionality in regions where the metal remains.
3Speed
If devices are scaled to smaller dimensions to improve performance, then higher switching speeds and current are achieved, but short channel effects increase and Vt control becomes more difficult
Solution Approach 1:
The patent transitions from a planar gate configuration to a three-dimensional wrap-around gate structure that controls the channel from multiple sides. This dimensional change enhances gate control over the channel, allowing for better Vt precision even as device dimensions are scaled down. The vertical field effect transistor structure with gate control from multiple directions mitigates short channel effects while maintaining scalability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by maximizing effective device width, reducing manufacturing defects, and simplifying connectivity schemes, while addressing the reliability issues associated with work function metal recess and encapsulation.
Implementation Method 1
filling the at least one recess with a high-k metal gate (HKMG)
Data Source
AI summary
A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin structure, and etching the dummy gate by a first amount to expose a top portion of the fin structure. The method further includes forming a first dielectric layer adjacent the exposed top portion of the fin structure, forming a spacer adjacent the first dielectric layer contacting the fin structure, and etching the dummy gate by a second amount. The method further includes depositing a second dielectric layer to encapsulate the remaining dummy gate, depositing an inter-level dielectric (ILD) over the second dielectric layer, depositing at least one hard mask to access the dummy gate, stripping the dummy gate to form at least one recess, and filling the at least one recess with a high-k metal gate (HKMG).