Self-Aligned 2D Metal Line Patterning for Sub-70 nm Pitch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The development of semiconductor technology has led to the challenge of achieving two-dimensional (2D) photolithography for forming metal lines with non-uniform line widths while maintaining a minimum pitch of less than 70 nanometers, which is difficult due to dimension shrinkage and photolithography limitations.
Innovation Solution
A self-aligned 2D patterning technique is proposed, which involves forming a mandrel layer, patterning it, and using spacer layers and multiple patterning processes to achieve metal lines with both uniform and non-uniform widths, while maintaining a minimum pitch of less than 70 nanometers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional photolithography is used to reduce component dimensions, then power and speed performance of ICs is improved, but manufacturing precision deteriorates due to diffraction limits and inability to form non-uniform line widths
Solution Approach 1:
The patent segments the patterning process into multiple discrete steps: forming mandrels with first line widths, depositing spacers to create second line widths, selectively removing portions, and forming final metal lines. This multi-stage segmentation enables independent control of different line width dimensions, achieving non-uniform line widths with precise control that overcomes the limitations of single-step photolithography
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional structured patterning by forming vertical mandrels and spacers with controlled thicknesses. The line widths are determined by dimensional parameters in different spatial dimensions (mandrel diameter, spacer thickness), enabling non-uniform line widths to be formed with high precision by controlling vertical dimensions through deposition processes rather than relying solely on lateral photolithographic resolution
2Manufacturing precision
If photolithography resolution is increased to maintain minimum pitch of less than 70 nanometers, then manufacturing precision is improved, but device complexity increases due to multiple patterning processes
Solution Approach 1:
The patent performs preliminary actions by forming mandrels and spacers with precisely controlled dimensions before the final metal line formation. The mandrels are formed with specific diameters and the spacers are deposited with controlled thicknesses that pre-determine the final line widths. This preliminary structuring with precise dimensional control enables the final patterning step to achieve minimum pitches of less than 70 nanometers with high precision, as the critical dimensions are already established in prior steps
Solution Approach 2:
The patent introduces intermediary structures (mandrels and spacers) that mediate between the photolithography process and the final metal line pattern. The mandrels serve as intermediaries that define the initial pattern, and the spacers act as intermediaries that create the final non-uniform line widths. These intermediary structures enable the transformation from simple photolithographic patterns to complex non-uniform line width patterns with precise minimum pitch control, distributing the complexity across multiple functional layers rather than requiring a single complex photolithography step
Data Source
AI summary
A method of semiconductor fabrication includes forming a plurality of mandrel recesses in a mandrel layer over a hard mask layer, performing a first patterning process on a spacer layer that is deposited over the mandrel layer to form a first opening pattern, performing a second patterning process to etch portions of the mandrel layer to form a second opening pattern, performing a third patterning process to form a third opening pattern in the hard mask layer based on the first opening pattern and the second opening pattern, and forming, through the hard mask layer, metal lines that are in a semiconductor layer under the hard mask layer and that are arranged in a pattern which corresponds to the third opening pattern.