Self-Aligned Metal Via Formation for Dense Semiconductor Interconnects
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, issues such as misalignment of metal vias, increased resistance-capacitance delay, electromigration reliability, time-dependent dielectric breakdown, and device defects arise, necessitating improved methods for forming metal lines and vias in dielectric layers.
Innovation Solution
A method involving selective deposition and etching processes to form recesses in dielectric layers, ensuring maximum contact between metal vias and metal lines, using sacrificial materials and dielectric layers to reduce misalignment and improve performance, including the use of low-k materials to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but misalignment of metal vias and increased device defects occur
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and depositing sacrificial material before final metal via formation. The sacrificial material is deposited conformally over the mandrel, then selectively removed to create precisely aligned via holes. This preliminary structuring ensures that subsequent metal via placement is automatically aligned with the underlying metal lines, eliminating alignment issues that typically arise when scaling to smaller feature sizes.
Solution Approach 2:
The patent uses an intermediary approach by introducing a sacrificial material layer as a mediator between the mandrel structure and the final metal via. The sacrificial material serves as a temporary structure that defines the via geometry and position during fabrication, then is removed to leave precisely formed via holes. This intermediary step decouples the alignment requirements from the final metal deposition process, allowing high precision even at reduced feature sizes.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but resistance-capacitance delay increases
Solution Approach 1:
The patent applies local quality by using different dielectric materials with different properties in different regions of the structure. Specifically, low-k dielectric material is used in the interconnect region where signal transmission occurs, while other dielectric materials may be used in isolation or support regions. This localized optimization reduces parasitic capacitance in the critical signal path without compromising the overall device structure, thereby reducing RC delay even as feature sizes are reduced and integration density increases.
Solution Approach 2:
The patent employs composite materials by combining multiple dielectric layers with different electrical properties. The structure includes a first dielectric layer with a first dielectric constant and a second dielectric layer with a second dielectric constant, where at least one layer uses low-k material. This composite approach allows optimization of the interconnect environment to reduce capacitance while maintaining mechanical support and isolation functions, thus reducing RC delay in high-density integration scenarios.
3Ease of manufacture
If conventional deposition methods are used to form metal lines and vias, then manufacturing process is simpler, but misalignment occurs between metal vias and metal lines
Solution Approach 1:
The patent uses preliminary action by forming the mandrel and sacrificial material structure before metal via deposition. The sacrificial material is deposited conformally over the mandrel, defining the via geometry and position in advance. This preliminary structuring creates a self-aligned template that guides subsequent metal deposition, ensuring precise via-to-line alignment without requiring complex alignment procedures during the metal formation step.
Solution Approach 2:
The patent applies self-service through self-aligned fabrication steps where the sacrificial material structure automatically defines the via position relative to the underlying metal lines. The conformal deposition process ensures that the sacrificial material covers the metal lines uniformly, and selective removal creates via holes that are inherently aligned with the lines below. This self-aligning mechanism eliminates the need for separate alignment operations, maintaining manufacturing simplicity while achieving high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces RC delay, electromigration reliability issues, and device defects while improving device performance by ensuring precise alignment and reducing parasitic capacitance.
Implementation Method 1
selectively depositing a sacrificial material over the metal line
Implementation Method 2
selectively depositing a sacrificial material over the metal line
Implementation Method 3
selectively depositing a dielectric material adjacent the sacrificial material
Implementation Method 4
the sacrificial material is trimmed using a plasma process
Implementation Method 5
a second dielectric layer is etched through to form first recesses exposing the sacrificial material, and the sacrificial material is selectively removed to form second recesses exposing the underlying metal lines
Data Source
AI summary
An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.