Self-Aligned Metallic Contacts in Semiconductor Structures
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to reduce transistor dimensions for higher integration density and performance while avoiding gate-to-via shorts and the use of highly resistive metal liners, which increase costs and degrade device performance.
Innovation Solution
A semiconductor structure with self-aligned metallic contacts that eliminate the need for contact lithography and etching, using metal semiconductor alloy layers atop the gate conductor and source/drain diffusion regions, and employing metals from Group VIII or IB with elements like W, B, P, Mo, and Re, without a highly resistive metal liner in the via contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are downscaled for higher integration density, then integration density and performance are improved, but gate-to-via shorts occur and manufacturing precision deteriorates
Solution Approach 1:
The spacer structure serves itself as the alignment reference for via formation. The via is positioned self-aligned to the spacer, eliminating the need for separate lithography and etching alignment steps. This self-service mechanism ensures precise via placement relative to the gate even as dimensions scale down, preventing gate-to-via shorts while maintaining high integration density.
2Reliability
If highly resistive metal liners are used in via contacts, then via structure stability is improved, but contact resistance increases and device performance deteriorates
Solution Approach 1:
The highly resistive metal liner layer is completely removed from the via contact structure. Instead of using traditional metal liners such as TiN, the via is formed directly in the dielectric material and filled with conductive material that makes direct contact with the underlying semiconductor structures. This extraction of the harmful metal liner eliminates the additional contact resistance while maintaining via structural integrity through alternative design approaches.
3Manufacturing precision
If contact lithography and etching steps are added to create precise via contacts, then via placement precision is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The via formation process is merged with the existing spacer formation process. The same lithography and etching steps that define the spacer pattern also define the via position. By combining these operations into a single self-aligned process, the patent achieves precise via placement without adding separate contact lithography and etching steps, thereby reducing manufacturing complexity while maintaining high precision.
Data Source
AI summary
The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.