Self-Aligned μLED Fabrication via Back-Side Exposure
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Solution Overview
Problem
The fabrication of micro light-emitting diodes (μLEDs) faces challenges due to strict alignment constraints as the size of μLEDs decreases, making it difficult to achieve precise alignment and increasing the complexity of the fabrication process.
Innovation Solution
A self-aligned process is employed for fabricating μLEDs, where a metal layer is patterned and used as an etch mask to etch both p-type and n-type semiconductor layers, eliminating the need for separate alignment steps and allowing for tighter misalignment tolerances and smaller feature sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multi-step alignment processes are used to fabricate μLEDs, then alignment precision can be achieved, but the fabrication process complexity increases significantly
Solution Approach 1:
The patent combines multiple alignment steps into a single self-aligned process where the p-metal layer serves as both the patterned feature and the alignment reference for subsequent etching steps. The p-type semiconductor layer is etched using the p-metal as etch mask, and the n-type semiconductor layer is etched using both the p-metal and p-type semiconductor as etch masks, eliminating the need for separate alignment operations.
Solution Approach 2:
The fabrication process employs self-alignment where previously deposited layers (p-metal and p-type semiconductor) automatically serve as alignment references and etch masks for subsequent processing steps. This self-service mechanism eliminates the need for external alignment equipment and manual alignment operations, simplifying the overall fabrication process.
2Length of moving object
If the size of μLEDs is reduced to achieve higher display resolution, then the display quality improves, but the alignment constraints become more strict and difficult to satisfy
Solution Approach 1:
The patent merges the alignment reference function with the functional metal layer, creating a self-aligned structure where the p-metal layer simultaneously serves as the electrical contact and the alignment template for etching both p-type and n-type semiconductor layers. This approach maintains precise alignment even as μLED dimensions are reduced.
3Manufacturing precision
If multiple separate alignment steps are performed to ensure precise alignment, then manufacturing precision improves, but the fabrication time and process cost increase
Solution Approach 1:
The patent performs preliminary patterning of the p-metal layer that inherently creates the alignment reference for subsequent etching steps. By pre-establishing the p-metal pattern that will serve as the etch mask, the process eliminates the need for separate alignment operations during later stages, reducing overall fabrication time while maintaining precision.
Solution Approach 2:
The patent combines multiple alignment operations into a single self-aligned fabrication sequence where the p-metal layer and p-type semiconductor layer together serve as the composite etch mask for the n-type semiconductor layer, eliminating the need for separate alignment steps and reducing total process time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process by reducing the number of alignment steps, enabling the production of μLEDs with improved alignment and smaller feature sizes without the need for expensive alignment methods, thus overcoming the challenges of strict alignment constraints.
Implementation Method 1
The negative photoresist is then exposed from the back side of the substrate, thus exposing the regions of the negative photoresist that are not masked by the p-metal
Data Source
AI summary
Embodiments relate to a micro light-emitting-diode (μLED) fabricated using a self-aligned process. To fabricate the μLED, a metal layer is deposited on a p-type semiconductor. The p-type semiconductor is on an n-type semiconductor and the n-type semiconductor is on a top side of a substrate. The metal layer is patterned to define a p-metal. The p-type semiconductor is etched using the p-metal as an etch mask. Similarly, the n-type semiconductor is etched using the p-metal and the p-type semiconductor as an etch mask. A negative photoresist layer is deposited over the patterned p-metal and the p-type semiconductor. The negative photoresist is then exposed from the back side of the substrate, thus exposing the regions of the negative photoresist that are not masked by the p-metal. The negative photoresist is then developed to expose the p-metal.