Self-Aligned MOS Contacts With Insulator Cap Against Gate Shorts
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Solution Overview
Problem
The fabrication of contact plugs in MOS transistors is prone to contact-to-gate shorts, especially as transistor gate pitches scale down below 100 nanometers, due to challenges in controlling critical dimensions and registration between gate and contact layers.
Innovation Solution
The implementation of an insulator-cap layer atop the gate electrode and within the spacers of MOS transistors helps minimize the likelihood of contact-to-gate shorts by electrically isolating the metal gate electrode from the trench contact, even in cases of misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional photolithography patterning is used to form contact plugs, then manufacturing process is simple, but contact-to-gate shorts occur due to misalignment and critical dimension control issues
Solution Approach 1:
The method performs preliminary patterning of the interlayer dielectric layer to form trenches before forming the gate electrode. This preliminary action establishes the contact region boundaries in advance, creating a self-aligned structure that prevents misalignment between contacts and gates, thereby eliminating contact-to-gate shorts without requiring tight registration control
Solution Approach 2:
The fabrication process is segmented into distinct sequential steps: first patterning the interlayer dielectric to form trenches, then forming gate electrodes, and finally filling trenches with conductive material. This segmentation allows each step to be optimized independently and ensures that contact regions are defined before gate formation, preventing alignment issues
2Productivity
If gate pitch is scaled down to increase transistor density, then productivity increases, but the likelihood of contact-to-gate shorts increases due to smaller critical dimensions
Solution Approach 1:
By preliminarily patterning the interlayer dielectric layer to form trenches before gate electrode formation, the method establishes contact region boundaries in advance. This self-aligned approach ensures that even as gate pitch scales down to increase transistor density, the contact regions remain properly positioned relative to gates, preventing shorts despite smaller critical dimensions
Data Source
AI summary
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.